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Recent content by sharon_f

  1. S

    Problem understanding System Verilog

    use a scope to check outputs.
  2. S

    Xilinix to Quartus "Library Conversion"

    xilinx bought hls from autoesl. o if you can get the original tool, you will have ability to generate code for ALTERA. but still you can generate a 'natural code' from the HLS tool, that you can try to synthesis in your quartus tool.
  3. S

    Confusion in using a pipelined arithmatic unit in feedback mode for recursive formula

    since this is a static calculation (c is constant) , then the formula can be pre-calculated at 0 time, for given c.

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