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hi
i am in need of DRC rules. i have been given the information that only fabs can give these set of rules. i want to perform drc for my design and layout. if any of you guys can provide me with a sample cmos library of say 0.35u process it will be very helpful. and also pls let me know if i...
Re: PLL design in Cadence ?
hi
if you are borrowing an architecture and change your transistors to the need of your specs then you could first freeze the specs i.e. convert the system level specs into the circuit level specs from the models and the libraries you have for your design. This is...
costas loop filters
I am need of designing a loop filter for costas loop.
I was said that loop filter is nothing but iir filter of order 2.
For example costas loop to track 25khz carrier frequency with .02% crystal oscillator deviation.
In this example a 6 bit nco is used.
After lpf section on...
Re: need a project
you can design any module like pipelining adders,or pipelining multipliers,or even alu this may be easy to do as ug project .
regards
shankar
cmos opamp design
hi guys
i m final yr student and doing a 2 stage cmos opamp design. i have completed the design of the individual stages of the opamp like the current mirror, diffamp etc, i want to know how to join/interface these two stages .i.e the op amp uses the amplifiers which r linear...
www.ocpip.org/university/biblio_main/
hi friends
im final year student. we are planning to work on network on chip . we should finish this project in 6 months. so can any one please give commands in selecting this project.
what network on chip do?
what level we can do on it?
any one please...
setup and holdtime
i am designing a synchronous adder .
my adder operating at 10 ns.
how can set setup time and hold time for flipflops
setuptime=?
holdtime=?
tclk=10ns.
how to make overflow on s4 bit adder
first check msb if its '1' then take two's complement and add the remaining bits with other number neglecting msb 's . if u get carry as '1' then take two's complement and append '1'with the msb
u beter choose asyn reset because your chip must be set to intial state when reset is applied . its like an interrupt and used in critical position so it should not depend on other signal like clock so prefer asyn reset
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