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Let me be very specific then, Let's say i have a FPGA(controller)having 50ms of bootup time. generating PWM of 200KHz regulating a Buck plant.Now, the idea is, without using any Hold up ckt for the FPGA Power supply, if the Power supply for the FPGA gets interrupted due to 'change' in Power...
The Plant is DC converter and the hiatus would be of 50ms in fact, during the startup. I was trying to figure out some alternative, aiming to avoid hold up cap.
Refer the attached schematics, I have a system as below, controller runs at 200 kHz. I have a requirement of interruption at the controller voltage for 50 μs, still during that I need to have the PWM running. I have one option to have hold circuit for the controller to stabilize the voltage, to...
No nothing specific.
I wanted to understand what would be optimum value to select for a specific scenario - consider the one i have described initially.
Please treat the schematic as a generic representation. My questions are also more or less to clarify myself on the Bandwidth aspect of the design. please ignore any other specifications for time being
Consider the attached schematics, The switching frequency is 250KHz, So, The cross over frequency be 250/5 = 50KHz. My ADC is 12bit able to sample at 1MS/s.(Ignore any other design spec for now). The doubts are below
1. For ADC selection-sampling rate the switching frequency should be considered...
Thanks for your insight on the Rbase and beta.
this circuit actually provides ADC reference voltage and at Vy node the actual max load is 20mA.
After writing the equations interms of Vbe and Vy(basically replaced Vo part) I was able to get convergence in Mathcad.
As it is stated R2 is useless...
I want to get the basic transfer function for Vy.
So, I just started putting the equations.
Later on I would add the temperature effects once the transfer function is obtained.
I have been trying to analyse the attached circuit. the equations which I write seems not to converge when I put in Mathcad. Below are the equations which I have for the circuit
for the node Vy, (Vy-Vx)/R2+(Vy/R1)-Ic_Q1=0;
V2-Vce-Vy=0;
Vo-Vbe-Vy=0;
Vo=(POS5v-Vx+Voffset_OA1)*Avd;
Finally I...
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