Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by seeker137

  1. S

    encyclopedia of electronic circuits

    mcclellan signal processing first torrent Gray & Meyer, Sansen, Razavi 's books are great.
  2. S

    Who is your idole in Analog Design?

    Gray & Meyer, Sansen, Huijsing, Razavi & Abidi, Steyaert ....
  3. S

    pll loop parameters calculation with matlab?

    Also, check out PLL design section at: www.circuitsage.com
  4. S

    Converge problem? how to solve it?

    Assuming that all the blocks have been simulated and are converging and non-convergence happens only when they are all put together: I will try the foll: 1.First iteration, relax all the options to low resolutions. Then save the operating point. Start the next simulation with tight resolution...
  5. S

    need help about metastability in PFD

    Metastability is basically when the output is in an undetermined state. If the PFD output is (from the flipflops) metastable that would mean that it is not tracking the input any more. This would cause a dead zone in the PFD response and cause jitter at the PLL output. Hope this helps.
  6. S

    how to reduce harmonics in ios

    Make sure of enough overdrive (cmos) or degeneration (bjt). degradation starts at overdrive/1.414. any overdrive problems leads to harmonics. slew rate limitation will also cause sine to be distorted, hence each stage should be biased with sufficient current. hope this helps.
  7. S

    How to calculate the settling time of VCO?

    Re: settling time of VCO sorry, not aware of any offhand.
  8. S

    How to calculate the settling time of VCO?

    Re: settling time of VCO I would simulate the vco by injection of an current impulse in the range of pico-amps (almost noise) and see how long it takes to reach steady state oscillation amplitude. Hope that helps.
  9. S

    how to assess if the stabilty analysis is necessary

    If there are multiple loops, in addition to above said paper's techniques, I would run a step response transient analysis treating the whole system as a black box. Based on the ringing at the output, damping factor, peaking etc can be determined. Hope this helps.
  10. S

    Track and hold simulatoin

    You can assemble an ideal T/H and run a sinewave through it and the actual design. Compare the ideal and actual design outputs and determine how many bits of accuracy are obtained. If you subtract the actual from ideal, you can get the non-idealities part of it (assuming they are all modelled)...
  11. S

    Mathematical Model of Phase Locked Loop in Matlab

    goto www.circuitsage.com plenty of articles and papers for pll models. hopecthis helps.
  12. S

    How a folded cascode can help to improve the cutoff frequency of a CMOS transistor?

    Re: extend cutoff freq? adding a cascode isolates the output node from the input node and thereby removing the miller cap from being seen at the output node, hence the improved freq performance. Cascode also provides more gain by increasing effective output impedance. Hope this helps.
  13. S

    CMFB in a cascode differential pair

    The cmfb voltage cnt has to be applied, as per the ckt schematic, such a way that you control the currents in the diff pair load so as to correct any cmfb imbalances. You can do that by applying the cmfb control voltage to pnt A . Hope that helps.

Part and Inventory Search

Back
Top