Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I hear you. And I agree that it's art. I know what I like in art, but trying to explain why I like a certain piece of art can be difficult.
Similarly, and taking the art metaphor a step further, when I see crappy layout, I know it. But explaining why it's crappy is sometimes difficult. This is...
I am interested in a Layout Design quality model that provides a taxonomy of layout design quality factors.
Does such a thing exist?
If not, how does one ensure/evaluate/enforce layout design quality?
Many industries have adopted various quality standards to assist in this endeavor. For...
Just to clarify, poly resistor dummies are used to ensure that the etch environment for the outside edges of the resistor array is the same as the etch environment between each resistor body. This can be a factor for critical resistors that must be matched to a high degree of precision.
I suspect "S/L" stands for substrate/latchup, which is what guardrings are supposed to help prevent.
I cannot explain your observed DRC issue except to wonder if the rule is from PO-to-active, or PO-to-contact. It could make a difference.
The better practice at my company is to always surround...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.