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pex bus
Hello,
I'm designing a chip with AMS high-voltage process. My LVS is matched. But when I run PEX, I got an error message:
*** Calibre finished with Error: bus error ***
Does anyone know what is the reason for this error? Thanks a lot.
calibre pex
I checked the PIPO.LOG file, no error is found.
Calibre PEX quit with such a message:
*** Calibre finished with Error: bus error ***
But what is a bus error and how to remove it? Thanks in advance for your help.
Hello,
I'm designing a chip with AMS high voltage 0.35um process. I am using calibre for verification. I have passed LVS. But when I do PEX, I got some warnings and PEX will be terminated. Here are the warnings:
WARNING: PEX BACKANNOTATION is obsolete. Please remove from your ruledeck...
high voltage cmos design with ams
Thank you so much for your help. Yes, the circuit is a simple inverter chain. The error only appears when I use symmetrical devices pmos20hs and nmos20hs in the first inverter.
Thanks.
problems faced during drawing cmos layout
Hi,
Thanks for the reply. My hit-kit version is 3.72. I can not try with assura because the version of assura is too low.
regards
hv cmos layout
I am drawing layout with AMS 50V high voltage CMOS process and I am using calibre from verification. I found one problem when I do DRC check.
I draw two inverters by connection the output of the first one to the input of the second one. I used nmos20hs and pmos20hs devices. I...
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