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try asap.asu.edu. Arm also provides a standard cell library and a design methodology for this academic 7nm PDK. See: https://community.arm.com/developer/research/b/articles/posts/bridging-the-gap-between-arm-physical-ip-and-academic-research
Re: what is the function of ICC(instruction cache controller)?
You should be able to get the details from a processor design manual/spec. At a very high level, instruction cache is the cache memory which stores the instructions that will be executed sequentially in a processor. The program...
Start by reading the following two books: Digital Integrated Circuits by Jan Rabaey and CMOS VLSI Design: A Circuits and Systems Perspective by Neil Weste and David Harris. Both are excellent textbooks, but I am not sure if they are good for self-study so I would also suggest trying to attend...
Here are a few, assuming that 'lower technology node' means FinFET based nodes (e.g. 14nm or below):
1. At sub-20nm nodes, min-pitch metals are printed using multiple-patterning (double or triple patterning), hence there are lots of restrictions on layout. Hence, achieving maximum density is...
Vt variation can be done by changing oxide thickness, but in advanced scaled technology nodes, this is achieved by varying channel doping or changing the gate metal work function (for high-K metal gate transistors). While drawing the layouts in a layout editor (Virtuoso in Cadence, for example)...
The information you're sharing is foundry-specific data most probably covered under NDA. It'd be advisable to seek this information from the foundry and not post questions/information in a public forum.
Two possible reasons:
1. If the mobilities of PFET vs NFET is 2:1, then going for a size ratio of 1.5:1 would be to change the delay slopes of rising/falling transition.
2. For recent technologies, strain engineering enhanced the mobility of electrons and holes. However, PFET and NFET respond...
I can give a quick qualitative explanation. I can probably add a quantitative explanation if there is a request and have time. Qualitatively, you can think of an energy barrier between the Source and Drain regions when the gate is turned off which prevents carriers from flowing across the...
First, you estimate is right that the your average power dissipation should be equal. Before getting into the details, how are you exactly measuring power. Is this an HSPICE simulation? Can you check your total current and see how that has changed between the two designs?
\[Ids=Is\frac{W}{L}{e}^{\frac{Vgs}{Vt}}(1-{e}^{\frac{-Vds}{Vt}}+\frac{Vds}{Va})\]
Use this equation to estimate how threshold voltage varies with supply voltage.
Delay is CV/I, so if you know all these values and current equation of a MOSFET (I), figuring out delay should be easy, right? Since this is an inverter, you want to make sure that the current through the NMOS and PMOS are the same, so essentially, size the PMOS so that you get the same current...
The equations are exactly the same as a regular MOSFET, because FinFET is just a MOSFET with a different structure. FinFETs help in improving electrostatics, so DIBL and Sub-Vt slope equations change from a regular MOSFET to a FinFET. Unless you're interested in them, you can use the same...
Please read the standard Digital VLSI textbook: CMOS VLSI Design: A Circuits and Systems Perspective by Weste and Harris. You should find all the details on how to read/write to the SRAM cell.
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