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Recent content by saurabhmimani

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    Confusion in pins of FPGA kit and Chip pins

    @ Tan yeah, but I am getting the error i have mentioned but I am getting the error i have mentioned because manual is saying you will get clock on pin77 but there is no 77 pin number in spartan 2 fPGA. I don't know am I able to convince what my problem is because when I copied the required...
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    Confusion in pins of FPGA kit and Chip pins

    operation manual for spartan-2 trainer example Yeah, I am completely agree with your point, I tried the same thing you have said but I am getting the following error- ERROR:MapLib:30 - LOC constraint 77 on CLK_4M is invalid: No such site on the I am coding the following simple blink_led code...
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    What in Bndry Scan given pinout tables of FPGA spartan 2

    Hi, I have found in datasheet of Spartan2 that in the table of Pins there is column of Bndry Scan, Can anyone help me by telling that what does it mean, why it is there. Thanking in advance.
  4. S

    Confusion in pins of FPGA kit and Chip pins

    pins of fpga hi I was using a spartan 2 kit in whose manual pin numbers of different IO"S are given as simple numbers as 77, 80 and so on, I don't know how to get pin number of spartan 2 FPGA respectively. I am using Universal DSP trainer from MTE Pune with Spartan 2 PQ208, manual can be...
  5. S

    Request for 16 QAM modulation verilog code.

    qam modulation hi kassytan, I was also requiring code for QAM in verilog can u help me by providing me code or at least some material which can help in designing the code. Thank you.
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    Resources for 128 QAM demodulator design

    128 qam hi,I haven't seen the demo for 16-QAM demodulator Design using System Generator and Simulink.but i think they will be helpful for me for my project, so can you please specify the link where I can get them. Thank you.
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    Design of QPSK receiver

    qpsk receiver I have to design a QpSK receiver and implement it on FPGA, I was trying to get good material for receiver but i can't . Can someone please help me by providing some material related to QPSK receiver and also related to different synchronization issues in receiver. Any help will...
  8. S

    How to generate random number between 44 to 55 ?

    Sorry as I am unable to get how you are generating random numbers, can you plz more elaborate it...
  9. S

    How to generate random number between 44 to 55 ?

    uniform distribution verilog command I think if you use a LFSR that have a very long period should give uniform distribution but as you are saying than it may not. However than what other way is to get uniform distribution?
  10. S

    How to generate random number between 44 to 55 ?

    random number between 55 to 77 in verilog using LFSR(Linear feedback Shift Register) u can generate pseudo random numbers out of them use 3 bits to 44 so that u will random numbers from 44 to 52, now add two different bits from LFSR register to this u will get random numbers between 44 and 55.
  11. S

    How to transmit the very high data rate ( > 120Mbps)?

    Yes you can, but feasibility will depend what is your purpose, what are requirement of transmission??
  12. S

    Difference in filter coefficients by MATLAB and by formula

    fir coefficients in matlab Thanks for reply. I also wants to know using this formula:- **broken link removed** (from wikipedia) How can I control cutoff frequency or stopband attenuation?
  13. S

    Difference in filter coefficients by MATLAB and by formula

    matlab filter coefficients Hi all, i was designing a FIR root raised cosine filter to use for my project of QPSK transmitter for pulse shaping purpose, first thing is I found following impulse response for rrc filter:- (taken from wikipedia) what I was planning to do is find h[nT] and than...
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    amplitude compensation in FIR filter

    thanks for reply. Can you please more elaborate on sinc compensation, why is it required and how to do it?

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