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Recent content by satyakumar

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    Advanced SystemVerilog, OVM and UVM Training in Hyderabad

    Neoschip Technologies Hyderabad is offering advanced training in VLSI design and verification covering 1) SystemVerilog based Verification , SoC system verification, Advanced Verification techniques using VMM (Verification Methodology Manual) OVM ( Open Verification Methodology), and UVM...
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    [Moved] SystemVerilog Training in Hyderabad

    system verilog training in hyderabad Full time course on Verification Using SystemVerilog - Hyderabad Venue: When: Batches starts on every Saturday at 11 AM Where: Hyderabad Cost: Rs. 10000 /- onwards (See below for details) Contact: training @ neoschip.in, +91-8886714111, +91-40-66567676...
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    How to start a startup in VLSI

    Hi Shweta, Were you successful in establishing VLSI startup, can you please mention your company name? Thanks Satyakumar
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    Urgent opening for embedded design engineers

    Hi Friends, I am Satyakumar from Neoschip Technologies,Hyderabad,India. We urgently require embedded design engineers with 0-2 years Experience. The candidate should have strong C/C++ and embedded Programming Fundamentals, and must have well in academics. Qualification: B.Tech/M.Tech in...
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    VLSI traing and project guidance

    Dear All, We are pleased to announce the we a group of people with well versed VLSI design expertise intended to offer VLSI training and Project guidance for fresh graduates. For more information kindly visit our website: www.vlsiprime.com Thanks and regards Satyakumar
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    Problem with using FIFO with Block Rams as memory type

    Re: Block Rams In fifo generation if we use distributed RAM does it going to impact the area as well? I know that it effects timing.
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    Problem with Xilinx DDR2 core while implementation

    xilinx ddr2 core I synthesized with syplify 8.8 then implemented with xilinx10.1i it works fine, but when I synthesized with synplify 9.4 and if I implement with 10.1i I get the fallowing map error. *************************************************************** ERROR:Pack:679 - Unable to obey...
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    Synopsys DC chip synthesis workshop!

    synopsys design compiler workshop Hi all, Does any one has DC 2007 workshop
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    Is derived clock from FPGA DCM is best?

    Hi all, I have question related to using FPGA DCM for driving external memory like DDR SDRAM. I am Implimenting a micro-controller in FPGA, it requires multiple clock for driving different interfaces. And it has one large size external memory (DDR SDRAM), I want to drive the DDR by a...
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    VHDL to VERILOG converter

    vhdl to verilog converter free download Hi, There is software XHDL which converts vhdl to verilog and verilog to vhdl, its licensed but can get evaluation license for 15 days. Thanks and Regards satyakumar
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    Upcoming PSL training @ CVC, Bangalore on 15th Oct

    Hi Aji_vlsi, Does this PSL training is for employes or freshers can also attend. Can you explain me in detail how it is benficial for employes and freshers. Thanks and Regards satyakumar
  12. S

    FIFO depth calculation

    asynchronous fifo depth Hi PPallavi, In this there are two cases we have to consider in determing the depth, 1)Best case: The incoming data is 80words /100clk i.e the data starts writing for 80clks and remains idle for 20clks. In this case for reading 80 words at the rate 8...
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    who dares takeover ultrasound receiever?

    Hi, The question is not clear, can you elaborate your question.
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    The function of metal layers in VLSI design

    Re: metal layers Hi, Wide metal layers will have more capacitance, this you can find from basic equation of capacitance. The wide metal layers decreases the resistance so, we should be carefull in choosing thickness. Randomly we can't come to conclusion. How much thickness we have to use...
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    Explanation of the contamination delay

    Re: contamination delay Hi gck, This time is genrally used in Flops, it is the amount of time taken to make a change at the Q from the moment when the clock edge is applied. This is very important in estimating the hold time. Thanks and Regards] satyakumar
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