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Recent content by sarath_mani

  1. S

    how to do RTL generation using external inputs..

    hi.. if there is any generic cparameters/values in VHDL or verilog to generate RTL, we give the values at the top module.. i wish to know how to generate RTL cores by giving the generic values from any external scripts or command prompt or from visual C++ windows application.. OR can any tell...
  2. S

    score board on system verilog

    Can anybody tell me about the score board concept in system verilog. :?::?::?: Can we generate a Reed-Solomon encoder using any System verilog cores. ?????
  3. S

    VLSI Job situation in USA from A fresh Masters student

    i ve 2+ years in FPGA prototyping and RTL development... I am thinking of a job or masters abroad.. im confused.. can anyone clear it out some...
  4. S

    Discussion on H.264 implementation

    Re: Discussion on H.264 Hi, im also on same ship, i need to implement 2D DCT on VHDL, can anyone help me...
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