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compile_ultra
When I run compile_ultra I get this warning:
Warning: Failed to read dw_foundation.sldb for the compile command. (UISN-44)
Should I be concerned? Is my design still been optimized using compile_ultra settings or is it just a regular compile with high effort?
Thanks
More output...
Just found out that from ncvlog user guide: For Verilog, you cannot probe arrays of variable data types to a VCD database. This includes Verilog memories, which are one-dimensional arrays of type reg.
Great! :(
Any other way?
My design has a 4kb memory unit and I need to capture its switching activity.
If I use:
$dumpvars(1, testbench.decoder0);
in my testbench, I should get all activity from all nets/registers in my design. However, I don't get any switching activity from my memory unit which is a 2D register...
viterbi decoder question
Hi,
There's a Viterbi HDL generator here:
http://viterbi-gen.sourceforge.net/
I was wondering if it is possible to generate an ip code with code rate 1/2? I wasn't sure on some of the inputs it takes in:
I know my traceback length is 5*(k-1) -> 30 -> 32
Has anyone...
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