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Recent content by santumevce1412

  1. S

    help reg this diagram

    how to design the circuit that generates the waveform given in attachment...
  2. S

    Interrupt latency is the time elapsed between what?

    Interrupt latency is the time elapsed between: 1. Occurrence of an interrupt and its detection by the CPU 2. Assertion of an interrupt and the start of the associated ISR 3. Assertion of an interrupt and the completion of the associated ISR 4. Start and completion of associated ISR...
  3. S

    NAND gate implementation for a function

    minimum number of 2i/p nand gate required to implement the following function Y = AB + CD + EF
  4. S

    please help, Design compiler problem

    design compiler system error Pls chek the path once.....
  5. S

    Help me design a 2bit up/down counter using only gates

    Design a 2bit up/down counter with clear using only with gates Pls dont write verilog or vhdl code...
  6. S

    Help me design a state machine to divide the clock by 3/2

    Design a state machine to divide the clock by 3/2. I/p frequency - 50MHz o/p requency - 33.3MHz
  7. S

    4-t0-1 mux in verilog

    verilog mux A 4-to-1 mux using if-else and case is given if-else statements if(sel_1 == 0 && sel_0 == 0) output = I0; else if(sel_1 == 0 && sel_0 == 1) output = I1; else if(sel_1 == 1 && sel_0 == 0) output = I2; else if(sel_1 == 1 && sel_0 == 1) output = I3; Using case statement case...
  8. S

    signal and variable.......

    Hi, what is the difference between signal and variable?
  9. S

    How to calculate setup and hold time?

    HI, I know setup and holdtime. I need some examples to calculate this.... I always find some difficulty in solving this timing issues. Pls help me
  10. S

    Implement a 8:1 MUX using 4:1 MUX.

    mux implementation Implement a two input and gate using 2-1 mux ??? pls help in this regard..................
  11. S

    MUX implementation in Verilog case statements/ if else statements

    A 4-1 mux written in verilog case statement will be implemented in hardware as .....? A 4-1 mux written using if else statements in verilog will be implemented in hardware as ...? My question is both hardware implementation is same or different? pls explain elaborately......
  12. S

    What do you mean by TSMC90LP, TSMC90GP, 130 LP or 130GP?

    what do u mean by TSMC90LP, TSMC90GP, 130 LP, 130GP
  13. S

    help regarding this diagram

    the above verilog code is working thank u for u r help i have asked one more question pls check u r inbox
  14. S

    interview questions regarding digital design

    Hi, Can any one post some interview questions on digital domain??? any site....??
  15. S

    Looking for info that explain BFM in details

    What is BFM... can any one explain in depth or any pdfs to read it....
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