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analog circuits
im doing the layout of a clocked comparator. simulation after parasitic extraction shows that there is an ofset of -40mV for the input transistors.any suggestions?
Also, any precautions while routing clock signal?
i designed a comparator for a sigma delta ADC and it is working fine.But i need to give the output to a latch through an inverter.after connecting a D latch to one of the outputs, the output changes.If latch is connected to both outputs, the circuit works fine.Can anyone help
zener diode
regulators, linear power supply
https://en.wikipedia.org/wiki/Zener_diode
https://www.st-andrews.ac.uk/~www_pa/Scots_Guide/audio/part5/page3.html
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