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Recent content by samvelc

  1. samvelc

    Verilog-AMS Simulator in Synopsys environment

    Hayk, There was a need for a single simulator for both verilog and verilog-A files. It's clear that it is possible to use co-sim - like XA-VCS, Nanosim-VCS, etc.
  2. samvelc

    Verilog-AMS Simulator in Synopsys environment

    Hayk, The subject is "Verilog-AMS Simulator in Synopsys environment", but not "Verilog-A ............" Hence, as you have already mentioned in your 2nd post, HSPICE doesn't support verilog files (it supports only Verilog-A) :)))))))))))))))) so your 1st post at least isn't so clear...
  3. samvelc

    what are remedies for IR drop

    IR-Drop Solutions: 1. Reduce the current consumption of the cell 2. Add more supply voltage pads 3. Reduce the wire resistance 4. Use multiple power layers 5. Add decoupling capacitors
  4. samvelc

    Verilog-AMS Simulator in Synopsys environment

    Could you please share any document which will show that 1.verilog files are supported by hspice. 2.verilog-a files are supported by vcs. Thanks.
  5. samvelc

    Verilog-AMS Simulator in Synopsys environment

    Hi all, I've just begun learning Verilog-AMS language and my first concern is which software tool to use in Synopsys environment. Please advice. Thanks in advance.
  6. samvelc

    Measurement of Static Noise Margin(SNM) for SRAM

    Hi All, I have some questions regarding measurement of SNM for SRAM (6T). Please see attached file. First, I have applied ramped signal to two inverters and got output signals (v(out1) & v(out2)). After that I have swapped X & Y coordinates for v(out1) signal and got the green curve...
  7. samvelc

    How to generate a digitized sinusoidal input signal for DAC?

    Re: Input signal for DAC Thanks, I will try it.
  8. samvelc

    How to generate a digitized sinusoidal input signal for DAC?

    Re: Input signal for DAC Thanks, But I need a digitized sinusoidal input signal.
  9. samvelc

    How to generate a digitized sinusoidal input signal for DAC?

    Hi all, I have designed a DAC. Now I want to test it. I want to apply a digitized sinusoidal signal as a input. But I do not know how to generate such kind of input signal. Could you please advice. Do you have a such example. Thanks in advance.
  10. samvelc

    12 bit and 20Mbps ADC & DAC

    Hi folks, I need your help. I'm going to design 12 bit and 20Mbps ADC and DAC. What structures to choose for ADC and DAC implementations? What structure will be more simple? P.S. Process node is 0.25um. Thanks in advance.
  11. samvelc

    H1B visa for analog/digital designer

    In what country do you live?
  12. samvelc

    stable sigma-delta modulator

    stable sigma delta mikersia, but how can I check with simulation is it stable or not ???? I need to probe some voltages may be...........or ...........I do not know.
  13. samvelc

    stable sigma-delta modulator

    sigma delta stability Hi mikersia, But how can I check (with simulation) the modulator is stable or not? Thanks.
  14. samvelc

    stable sigma-delta modulator

    sigma delta modulator stable Hi all, What does it mean - the sigma-delta modulator is stable. And how it can be check? Thanks.
  15. samvelc

    Oversampling sigma-delta analog-to-digital converters modeli

    Hello, I need the follow book: " Oversampling sigma-delta analog-to-digital converters modeling based on VHDL" Baraniecki, R. ; Dąbrowski, P. ; Hejn, K. Please, help me.
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