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Verilog-AMS Simulator in Synopsys environment

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samvelc

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Hi all,

I've just begun learning Verilog-AMS language and my first concern is which software tool to use in Synopsys environment.

Please advice.

Thanks in advance.
 

samvelc

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Hspice, vcs

Could you please share any document which will show that
1.verilog files are supported by hspice.
2.verilog-a files are supported by vcs.

Thanks.
 

haykp

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samvelc

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Hayk,

The subject is "Verilog-AMS Simulator in Synopsys environment", but not "Verilog-A ............"

Hence, as you have already mentioned in your 2nd post, HSPICE doesn't support verilog files (it supports only Verilog-A) :)))))))))))))))) so your 1st post at least isn't so clear.

Concerning VCS. Till now I didn't find any document shows that VCS is supporting verilog-A files.


Thanks.


HSPICE supports only verilogA files. It doesn't support verilog files.
Think the following links can be helpful, they are showing HSPICE support for verilogA files:

https://www.edaboard.com/threads/98259/
Can I co-simulate Hspice with verilogA components
https://www.synopsys.com/links/hspice_news_spring05.html

For VCS-verilogA please refer to Mixed Signal Users Guide of VCS ( sorry cannot share).

Thanks,
Hayk
 

haykp

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Samvel,

Now I see where from your confusion comes. So you want to see a single tool which supports files with both verilog+verilogA in them.
Let me expand more here to make it clear. If you want to simulate veriog and verilogA models, then this is called mixed-signal simulation as verilogA is used to model analog circuits, verilog for digital circuits. Such mixed-signal simulations are supported by VCS. Refer to VCS mixed-signal.pdf “Part3: Verilog-AMS-SPICE Mixed Signal Simulation.”

Now the important point, during this simulation VCS internally calls analog simulator e.g. HSPICE (or XA, Nanosim) to simulate the analog part: verilogA models.
Therefore saying that VCS supports verilogAMS, this is not such a “correct” as you cannot simulate pure verilogA models only using VCS simulator digital part. It is more “correct” to say that VCS support mixed-signal simulation which means that while simulating digital and analog designs VCS is able to call internally analog simulator. One more thing as VCS support mixed-signal simulator, hence there is no need for VCS to support pure verilogA models, as such tool already exists in Synopsys and no need to do the same job twice.

In my first post I stated
1) HSPICE supports veriogA
2) VCS support verilog.
In second post: VCS support mixed-signal simulations.
Sorry for creating confusion.

Custom Designer latest release (very soon) provides support/interface/debugging options for such mixed-signal simulations.

Regards,
Hayk
 

samvelc

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Hayk,

There was a need for a single simulator for both verilog and verilog-A files.
It's clear that it is possible to use co-sim - like XA-VCS, Nanosim-VCS, etc.
 

ali kotb

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hello all
which is better XA or nanosim for coded verilog block and a spice ct. level netlist block ?
 

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