Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by samuelyou

  1. S

    how to select process for a PMU output +-15V, +-20

    I'd like to design a PMU, boost 15V, buck-boost(inverting) -15V; then two charge pump output +-20V. But most HV process use the N buried layer to do the HV MOS, all the LV5V device can isolated by HVNWELL and N buried layer. But how to isolated the HVMOS? So I confused about the process...
  2. S

    ldo buffer design issue, pls help

    Thanks for your reply, I will check the gain margin. Added after 7 minutes: The waveform looks like a trangle rather than a sine wave. And the EA works like a comparator, the output is always saturate. The buffer(source follower) output cannot follow the EA output very well. Thanks for your...
  3. S

    ldo buffer design issue, pls help

    Thanks for all your help! Do you have some papers about the large signal vs small signal stability? If you are convenient, pls share some, thank you!
  4. S

    ldo buffer design issue, pls help

    yes, I use the VCVS with gain 1. But I confused with the STB simulation result, the phase margin is enough, why the output oscillate? I thought about the slew rate of the EA and the buffer, it seems that the buffer can not follow the EA_out quickly. So I change the buffer to a VCVS. Added...
  5. S

    ldo buffer design issue, pls help

    I would like to design a ldo with buffer, but some strange thing happened when I added the buffer. The phase margin is ok, but the transient simulation result show the output is oscillation. When I change the buffer to a VCVS, the transient oscillation disappear. Please help to analysis why the...

Part and Inventory Search

Back
Top