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https://obrazki.elektroda.pl/34_1328100828.png
these are my simulation results................
---------- Post added at 22:55 ---------- Previous post was at 22:54 ----------
https://obrazki.elektroda.pl/34_1328100828.png
these are my simulation results................
---------- Post added...
dflipflop desc. Is in submodule program and it has the same coding
---------- Post added at 11:59 ---------- Previous post was at 11:57 ----------
in the simulation results it is showing red crosses.
these are my codes
entity csadd is
Port ( a,b,CLOCK : in STD_LOGIC;
S:OUT STD_LOGIC;
cout,cin:inout std_logic);
end csadd;
architecture Behavioral of csadd is
component DFLIPFLOP is
Port ( D,CLOCK: in STD_LOGIC;
Q : out STD_LOGIC);
end component;
signal...
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