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Thank you for the response.
The user manual mentions the below:
params HAL {gated_clock_domain_same_as_master="no"|"yes"}
When this parameter is set to yes, HAL considers the clock generated from clock gating to be of the same domain as that of its master clock. If this parameter is set to...
Hi,
I am doing LINT analysis using cadence HAL. The below mentioned error is generated:
halstruct: *E,CLKDMN Signal from clock domain '%s' is crossing into domain of clock '%s' at flip-flop '%s' without proper synchronization
params HAL {gated_clock_domain_same_as_master="yes"} is set as clock...
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