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Recent content by sairasalim

  1. S

    What is the syntax error in the verilog prog in declaring the s and d as arrays.

    module split(x,s,d,N); input [4:0]x[4:0]; input N=4; inout [4:0]s[0:4]; inout [4:0]d[0:4]; reg [4:0]s[0:4]; reg [4:0]d[0:4]; reg i,j; initial begin for(i=0,i<N,i=i+1) begin for(j=0,j<N,j=j+1) begin if(j%2== 0) [i]s[j]=[i]x[j]; else [i]d[j]=[i]x[j]; end end end endmodule...
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