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Recent content by sachinagg77

  1. sachinagg77

    Programmable Gain Amplifier

    Dear Prince Thanks for your detailed explanation. I understand that any high impedance node will pick up noise. The circuit is fully differential. Do you think it will help reduce the impact? I searched but was unable to find any technical paper that refers to the unused capacitor connections...
  2. sachinagg77

    Programmable Gain Amplifier

    switched capacitor programmable gain amplifier Dear All I am presently designing a switched capacitor based PGA. The gain is set using a variable feedback capacitor. Many capacitors are connected between the op-amp input and the output. Suitable feedback capacitance is selected using switches...
  3. sachinagg77

    problem about LDO design-change of ESR changes pole

    Re: problem about LDO! Flying I saw your circuit. I think you will have serious problem in securing enough phase margin with this circuit for all corners. You have three high gain stages...each will generate a pole. The external capacitor in your simulation is 10u but it might change by as...
  4. sachinagg77

    Noise Analysis of Switched Capacitor PGA

    noise analysis switched-capacitor I designed a switched capacitor PGA for gain settings of 0dB to 12dB. To check the thermal/flicker noise contribution of this circuit, I used .NOISE analysis (spectre). The circuit was kept in closed loop. I would like to request for feedback on the...
  5. sachinagg77

    How to advance the PSRR?

    Hello Using Ahuja's compensation technique will help to improve the PSRR of a two stage op-amp. Here is the document ieeexplore.ieee.org/iel5/4/22592/01052012.pdf?arnumber=1052012 Hope it helps. With Regards Sachin
  6. sachinagg77

    Low Power Pipeline ADC

    Regarding (2), I think that voltage swings relate to power. Due to large swing requirements, scaling down the output devices is not feasible (will lead to increased VDS requirements). Therefore, large devices are necessary and this leads to increased parasitics at the output and hence more power...
  7. sachinagg77

    Oscillations at a phase margin of 90?

    AC simulations dont always present the true picture. First, some of the poles and zeros might not be visisble in the AC simulation (for example, closely placed zero-pole pair) which might have detrimental effect on settling behavior. Secondly, AC analysis are for a particular set of operating...
  8. sachinagg77

    Switched Capacitor Sample and Hold Circuit: KT/C Noise

    flip‐around sample‐and‐hold Dear JiangXB Thanks for your response. I agree with you that the KT/C noise should equal "KT/Cs". I am slightly confused about the KT/C noise presented in the following document (page 242). Please note that this is a different SH architecture (flip-around)...
  9. sachinagg77

    Low Power Pipeline ADC

    Dear RFSystem Thanks for your comments. Let me reiterate your points to make sure that I understand them properly. 1) Using minimum sizes will lower down the parasitics and thus reduce the need for power to drive these parastics 2) I am working with VDD=1.8V (min=1.6V). My swing requirements...
  10. sachinagg77

    Switched Capacitor Sample and Hold Circuit: KT/C Noise

    sample and hold capacitor Thank you for your comments. Dear Jiangxb I have an amplifier circuit. It is not an integrator. In phase 1, the capacitor CS samples the input via a switch. In phase 2, the charge is transfered to another capacitor CF (feedback capacitor). This capacitor, along with...
  11. sachinagg77

    Low Power Pipeline ADC

    low power pipeline adc Dear Friends I am looking for ideas on designing a low power pipeline ADC. I am considering sharing op-amps between consecutive stages. Any feedback or suggestions on this will be highly appreciated. Regards Sachin
  12. sachinagg77

    Switched Capacitor Sample and Hold Circuit: KT/C Noise

    kt/c noise Dear Friends I would be grateful if someone could explain the KT/C noise (input referred) contribution of Sampling Capacitor (CS) and feedback capacitor (CF) for the standard two capacitor S/H implementation (not the flip around architecture). Regards Sachin
  13. sachinagg77

    Impact of load capacitor on the slew rate of a standard two stage op-amp

    Hello Can someone please explain the impact of load capacitor on the Slew Rate of a standard two stage op-amp? In addition, can the use of cascoded miller compensation improve the slewrate performance of an op-amp? I will appreciate if someone can point out the method to derive the slewrate...
  14. sachinagg77

    Reference Buffer: For high Speed pipeline ADC

    Thank You Btrend. I apologise for the delayed response. I understand the first point you mentioned but could not understand the second one. What do you mean by using "Current Mirror" as buffer? Could you please elaborate a bit? Regards Sachin
  15. sachinagg77

    Weird THD results of a SH circuit

    Dear Friends I designed a SH circuit as first stage for my pipeline ADC. I use Cadence Analog Design environment and spectre for simulations. I performed a DFT analysis on data obtained by transient analysis (coherant sampling, strobeperiod option used). The plot looks fine. I also included...
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