Low Power Pipeline ADC

[sachinagg77]

low power pipeline adc

Dear Friends

I am looking for ideas on designing a low power pipeline ADC. I am considering sharing op-amps between consecutive stages. Any feedback or suggestions on this will be highly appreciated.

Regards
Sachin

 

[rfsystem]

The story is very simple:

Design w/o considering mismatch effects. Then you can use near minimum area devices.

Tolerate miss decisions in comparators because of noise. If your design have error correcting headrooms.

Pipeline is ideal to implement error correction and calibration. All new sub-100fJ/Decision result are based on these two items.

 

[sachinagg77]

Dear RFSystem

Thanks for your comments. Let me reiterate your points to make sure that I understand them properly.

1) Using minimum sizes will lower down the parasitics and thus reduce the need for power to drive these parastics

2) I am working with VDD=1.8V (min=1.6V). My swing requirements are also considerable. This prevents me from reducing the output amplifier transistors: Large transistors => large parasitics => large power

3) I understand that the comparator specs are considerably lowered due to the digital error correction but my adc is a high resolution circuit and I need to resolve at least 2 effective bits per stage. This allows very little margin to play with comparator accuracy.

I am looking forward for your further comments.
Regards
Sachin

 

[rfsystem]

To

1) Yes

2) No, voltage swing does not relate to power. You can scale the device to the driving conditions.

3) If a correcable architecture is selected there is no accuracy spec for the comparator. Other the correction headroom should include the maximum mismatch or offset voltage, or either in which domain it operate. Still noise could rised because only the added or subtracted residual should be accurate after calibration. But still settling time violations are acceptable if they result in linear error factors.

 

[sachinagg77]

Regarding (2), I think that voltage swings relate to power. Due to large swing requirements, scaling down the output devices is not feasible (will lead to increased VDS requirements). Therefore, large devices are necessary and this leads to increased parasitics at the output and hence more power to drive them.

What is your opinion?

Regards
Sachin

 

[rfsystem]

Regarding (2) there are two counteracting effects for the total power consumption.

1. If nearly 100% of the supply could be used for signal processing the required DC is minimum.

2. For output stage design it is true if you want to approach the supply up 10% or 5% you need in the same extend bigger output device which increase the driving power for the same bandwidth.

If you could estimate this numbers from you actual circuit architecture the next step is to find the minimum power. It could be for instance 87.3% of the supply.

 

[DZC]

This question is too general...