Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I want to perform complex multiplication using Verilog. Here I have called a module inside an always block. But, I got an error in the line "adder d(acc,m,clk,rst,out1);" (line 29) as error: syntax error near "adder". I tried to solve this problem in different ways but still showing the same...
xout has a size of
output signed [15:0] xout [0:15];
in other words if I display xout values in 16-bit wise
[255:240] xout to [15:0] xout
0000010000001100
1111101010101110
1111110101001101
1111111110001101
1111110101000101
0000001011000110
0000000100011001
0000001101011101
1111101010011100...
Hi, I am new to HDL. I have downloaded a verilog code for the CORDIC based implementation of FFT https://github.com/JoshuaEbenezer/FFT-cordic-HDL. A project_report.pdf file is also available in the given link. The design basically computes the 16 point Radix-2 DIF FFT algorithm. According to the...
Hi,
I am writing the verilog code for CORDIC (COordinate Rotation DIgital Computer) in xilinx vivado. For that I need 45, 26.565 degree rotation angle in 32-bit binary form. After searching in the internet I got 45 degree angle can be represented as
assign z[00] =...
Hi, I am new to verilog-hdl design. I am using xilinx vivado in order to synthesize and implement the design. The design basically a FFT algorithm. I want to calculate the percentage of "Fully used LUT-FF pairs" used by the design. After implementation by selecting a FPGA device the total Fully...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
