Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by RubyS

  1. R

    Regarding Mtech Project

    I am doing MTech in Applied Electronics.I need help me selecting topic for my final year.please help
  2. R

    How to Design Truncated counter using 3 flip flops

    actually i got this in my Lab model exam..i remembered d circuit of up down counter so did something with that..but didnt get d correct output
  3. R

    How to Design Truncated counter using 3 flip flops

    Can anyone help me designing a truncated counter in structural modeling using 3 flip flops.
  4. R

    what does this operator stands for ^=

    I was reading some paper regarding galios field and a snippet of code was given as shown below for i = 0:7 for j = 0:7 result [i+j] ^= a[j] & b[i] in this i m not able to understand the operator "^=".Is this some reduction operator..kindly help
  5. R

    Reed solomon encoder output

    Reed solomon DEcoder input I am implementing a reed solomon decoder but i am not able to understand what input i must give to the d decoder,waht is the corrupted received codeword.strictly i am doing only the decoder so i have to input the R(x)=c(x)+E(x) to the decoder.Kindly help asap
  6. R

    Need help for in the matlab code of optimum receuver!

    I m a starter in matlab.I have to submit a code for optimum receiver.However i am not able to run the code..I am attaching the code..Kindly help asap.
  7. R

    Difference between the Delay in verilog

    Whats the differnce between #10 b=0; and b=#10 0;
  8. R

    Simulation problem in Verilog

    Hii.i am trying to simulate a verilog code.i am using MODELSIM SE 6.5..but its coming as no design loaded and shows as below..what does it mean ** Error: (vopt-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver". # No such file or directory. (errno = ENOENT) # ** Error...
  9. R

    NEED HELP To SIMULATE VERILOG CODE

    Hi am very new to verilog..however i have to submit a code for my assignment and from net i got d code for reed solomon codec.I am using Xilinx 9.2i and MODELSIM SE 6.5 but i m getting Illegal redeclaration of 'inv_gf256' ,Illegal redeclaration of 'gf256mult' in this code..kindly help me asap...
  10. R

    FLOATING POINT ARITH VHDL CODE

    hey it takes less thn a day to register in opencore
  11. R

    Vhdl code for reed solomon decoder

    Hii I m doing a project in RS Decoder in vhdl..I m very new to vhdl .Can you send me the code for it..thx 4 d help

Part and Inventory Search

Back
Top