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Re: verilog question
3 signal sensitivity lists are possible.. They are synthesizable in many cases.. eg. a clock, a reset and a start willl be or ed together and given the appropriate pin of a d ff.
the difference is that in the first case the evaluation of the RHS takes place immediately but assigment after 1 ns. In the second case evaluation itself done after 1 ns
dpll pdf
check out these sites... i think this is what you asked for..
www.es.lth.se/home/peter/ html/papers-pdf/thomas-ecctd01.pdf
www.sss-mag.com/pdf/dpll.pdf
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