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Hdl coding from the synthesis point of view

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rsjgs

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synthesis help

can anyone give me an alternative for the use of loops? Also any guidance on hdl coding from the synthesis point of view?
 

synthesis help

maybe the reference of synthesising tooles will you
hint
for example Xilinx ISE's reference ,you can get it at the Help , or company's web..........
 

synthesis help

module (clk,count,datain,dataout);

input clk,datain;

reg [3:0] count,internal_reg;

always@(posedge clk)
count <= count + 1'b1;

always@(posedge clk)
if(count <= 4'b1111)
internal_reg[count] <= datain;

endmodule

this is one way of using the loops. I'm sure this is synthesizable.
 

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