Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi timof,
Thanks again for replying, but the error still persists with your idea.
I also tried to put this definition in the emitter instead, but still the same error.
This is very strange.
What it could be?
Dear timof,
Thank you very much for your reply and clarifications.
With the approach you gave me, the error now is that base and emitter are shorted.
CT_EM = CT AND emitt
CONNECT M1 emitt by CT_EM
CT_CL = CT AND coll_pin
CONNECT M1 coll_pin by CT_CL
CT_BS = CT AND base
CONNECT M1 base by...
OK my dear colleague timof!!
Thank you very much for your reply.
Let's see what we can do debugging this.
This is my vertical npn bjt device.
Yellow color is SN (shallow n layer)
Red color is SP (shallow p layer)
Thick yellow line is NW (the n-well)
Blue is M1 (metal 1)
Checkered White is CT...
Does anyone here have experience in writing LVS check rule file using SVRF from Calibre and can give me some help to find the connectivity error in my LVS code?
I am coding the device definition for a vertical npn BJT device.
As long as someone does candidate to help me I share my code.
Thanks!
Hmm.. I am not sure whether I understood your question correctly or not.
In general, standard CMOS process has 5 corners (FF, FS, SS, SF and TT).
FF and SS take into account full variation of both nmos and pmos.
Basically the VT and Idsat changes in both devices to match fast (for FF) or slow...
Hello niteshtripathi!
First, take a look at this picture:
From this picture, you can see that the 'fast' for FF and FS corners are not at the same coordinate.
So you can not expect that FF and FS for the n-type lead to the same results. :)
This is because the FS is a mixed mode corner so it...
@simplsoft, as it was already mentioned, mathematically speaking, filters and amplifiers perform different functionalities.
Therefore, they are different in essence.
This is the first step you need to understand. If you don't see this mathematical difference, we can not make progress.
Active...
Yes, I understand your point. In essence, ice and water can be seen as the same, if you want, and I agree with you.
But the point the others are trying to make (which I think is also very important to consider) is basically in what you want to do.
For instance, consider you have a signal with...
What is the difference between water and ice?
We use water to quench the thirst and the ice to refresh a drink.
But if we eat ice we can also quench the thirst and drinking water on a hot day is also refreshing. <:)))
You define how you want to use both, the same with amplifiers and active...
Who said that it "has to be bigger than the first stage?"
Please, provide me what books/references that put so strong affirmation.
Of course, everything depends on what kind of application your aiming for.
There are a lot of reasons you want to burn more current at the output stage: increase...
A very efficient technique to design analog ICs is the gm/ID methodology.
In this case, you need to calculate what is the tail current that you need given the required gm at the differential pair input you want.
Once you have calculated this, you can put an ideal current source for first order...
This is not your main issue.. The point is that you are not doing this in the right way. Just check whatever book on Analog IC design and you will see what I mean on my previous post. Bias your circuit properly and it should work. Good luck.
Look, in your first circuit you are tying the gate of M18 to VDD.
In principle, this is not the correct way of biasing because you want M18 to behave as a current source and create a virtual ground for balancing the current at each branch.
Basically, what you are doing is dropping the drain...
Believe me, tweaking your circuit like this is not the best practice.
Your first circuit works as well. It's much better to have a current mirror as a load in your differential stage.
If you want to get more help from us, you should give further information such as: VDD, threshold voltages and...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
