Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
My design include memory and analog IP . I don't know how to arrange power and gnd lines in floor-plan. is it separate digital and analog power lines? It is important to design power-gnd plan on ASIC. Who have reference data or book?
I am follow this method. My design is core limit, due to reduce area that some core power ring and pad power ring be placed same area.
I want to connect both power ring. I don't know this method disadvantage.
PS: It is include analog pad.
sdf_annotate
$sdf_annotate ("sdffile.sdf", "module_name", ,"sdffile.log");
That "module_name" must met your design !!
Ex: module testbench();
m1 m1_0(............);
m2 m2_0(............);
...
Why to use two D-type flip-flops in series to capture an asynchronous input ?
Why not to use one D-type filp-flop?
Where can get reference paper or data ?
By RMM, at the flip-flop which captures the asynchronous input, there is a probability of metastability occurring.
Why ??? I don't know what reason to use.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
