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Hello,
I have a problem with high amplitude PDM to PCM conversion on the hardware.
Actually, I m using a digital mic to capture the sound, it provides me the data in PDM format. That data is fed to Sigma-Delta modulator to covert it into PCM. Then it is processed and again converted...
actually one of the senior member in my company use logical or/and instead of bitwise, I prefer bitwise so i wanted to know first the complications with the former before i go and talk to him about it :)
hello,
As per synthesis/fabrication point of view, which among logical AND/OR (&&/||) or Bitwise AND/OR (&/|) is better ... given that operation is being performed of single bit stream of data.
I m sorry ... that is no way related to my problem ...
I don't want to dived by 7 ... !! i have problem compiling code ...
And i've already mentioned that I m running it on Windows ... liniux command won't work ...
Hello,
I m trying to synthesis an asic code using iverilog ... but i m not able to simulate the filelist in one go ... it keeps showing that .h file is not found, and keep denying that the top file which i've defined is not the top file ...
Has any one faced this issue, i m using the...
Re: SPI in VHDL
hello, the link you've provided is probably not full ... coz its not pointing to any location ..
if u can plz generate a tinyurl from tinyurl.com or any such site ... that would be helpful
Added after 3 minutes:
i've found the link ... here it is
**broken link removed**
spi flash memory
hello,
I've designed, an SPI core for code loading on my chip. Now i have to test it in the master mode. for that i m looking for a Spiflash (ex. winbond ) interface.
If any one has a verilog code for that, I would be really really grateful.
thanks in anticipation :)
yes that true ... VLSI industry is going through a tough time these days ...
many big companies reduced their work force and some have shut down including big names like connexent and all.
start ups have suffered severely, and very few of them managed to survive.... !!
With the profit...
hello,
can any one plz tell me the precise difference b/w contention latency and serialization latency ...
and what are the other type of latencies, which one come across in system on chip ...
thanks in anticipation ... :!:
hello,
I m working on chip verification and have just started learning System verilog for that purpose ...
I came across the term RPS (Rock Paper Scissor) verification ...
can any one please tell me, what is that ... and suggested me some good reading material for the same ...
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