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I suggest you search for the following ebooks on Internet (emule) :
*- Arithmetic and Logic in Computer Systems (Wiley Series) by Mi Lu
*- Digital Computer Arithmetic Datapath Design Using Verilog HDL: CD-ROM included (International Series in Operations Researchand Management Science) by...
Clock domain synchronization is not a simple solution, because of the metastability problems. This problem is quite large and you should investigate a little on Internet to understand what it is. However, there is two solutions :
1 - for a single signal use 2 cascaded flip-flops, synchronized...
Signal and port assignment are discarded during the synthesis process. This feature is only destined to simulation and modeling purposes. This is the reason why you get two different results.
The only thing you can give a fixed value during definition is a constant.
In my point of vue, if you get warnings about ouputs stuck at gnd or vcc, it might reflect the fact that your design generates always zero or one on the corresponding pins.
The warning is here to make you verify if you do not have any misconception in your design (vhdl or schematic), that...
Re: divide by 5 clock
The last response is right.
You can see it another way : imagine you have a counter by 5 (0 to 4). This defines 5 cycles. The clock is generated by testing the output of the counter.
From 0 to 3 the output would be 0. For the fith value (4), the output would be 1.
Yeah, I think the best solution is to use a DLL or PLL macro with proper settings in order to make one frequency from the other.
Have a look at the datasheet of your FPGA. There are also many examples with all FPGA manufcturers (Application Notes).
Hi, I get the following log, can you help me?
Auto-connect not enabled - Not connecting (Try enabling auto-connect on the ICD2 settings pages.)
Downloading Operating System
Connecting to MPLAB ICD 2
Setting Vdd source to MPLAB ICD 2
ICDWarn0020: Invalid target device id...
Ooops, I thought Nokia uses ARM architecture with AMBA bus controllers, not Intel architecture! Quite interesting... How did you get this info?
Added after 6 minutes:
Reconfigurable processor is a nice paradigm for new processors architecture. Imagine you can build your own instruction set...