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Recent content by robinh

  1. R

    Installing Cadence products on FreeBSD

    bsd cadence It is an os or a simple tool to perform compatibility ? Any one test-it ?
  2. R

    Number theory and FPGAs

    Hi, You would better make a search for good ebooks about this subjects. I saw many of the on Internet (emule).
  3. R

    which FPGA kit is best for beginners?

    celoxica rc10 Hi, the Celoxica RC10 should be a good start point.
  4. R

    thesis on multipliers

    Hi, I suggest you search for the following ebooks on Internet (emule) : *- Arithmetic and Logic in Computer Systems (Wiley Series) by Mi Lu *- Digital Computer Arithmetic Datapath Design Using Verilog HDL: CD-ROM included (International Series in Operations Researchand Management Science) by...
  5. R

    How to initialize the memory locations to "00" during reset condition ?

    Re: memories A memory that is initialized during the reset is not a memory but a register...
  6. R

    How to read MP3 files on SD card ?( DE2 board mp4 player project)

    de2 sd card Hi, the design board should have some kind of reference application or demo in which you can take what you want to build your own design. look at the accompanying datasheets and documents.
  7. R

    Multiple clock domain sync

    Clock domain synchronization is not a simple solution, because of the metastability problems. This problem is quite large and you should investigate a little on Internet to understand what it is. However, there is two solutions : 1 - for a single signal use 2 cascaded flip-flops, synchronized...
  8. R

    intialization in VHDL

    Signal and port assignment are discarded during the synthesis process. This feature is only destined to simulation and modeling purposes. This is the reason why you get two different results. The only thing you can give a fixed value during definition is a constant.
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    warning of output pins stuck at gnd or vcc (CPLD)

    In my point of vue, if you get warnings about ouputs stuck at gnd or vcc, it might reflect the fact that your design generates always zero or one on the corresponding pins. The warning is here to make you verify if you do not have any misconception in your design (vhdl or schematic), that...
  10. R

    How to Convert from "STD_LOGIC_VECTOR to STD_LOGIC&quot

    what is std logic vector Use a signal for the input and for the output. You do not need any function to do this. A simple assignment should be sufficient for both of them.
  11. R

    How to generate a pattern for generating divide by 5 clk ?

    Re: divide by 5 clock The last response is right. You can see it another way : imagine you have a counter by 5 (0 to 4). This defines 5 cycles. The clock is generated by testing the output of the counter. From 0 to 3 the output would be 0. For the fith value (4), the output would be 1. This is...
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    How to get two different frequency signal synchrously?

    Yeah, I think the best solution is to use a DLL or PLL macro with proper settings in order to make one frequency from the other. Have a look at the datasheet of your FPGA. There are also many examples with all FPGA manufcturers (Application Notes).
  13. R

    433MHz RF link for under $10 BOM?

    Have a look at abacom (www.abacom-tech.com) or aurel (www.aurelwireless.com) modules. They surely have what you need. RobinH
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    Project to replace CY7C64613 in the ICD2

    Hi, I get the following log, can you help me? Thank you Auto-connect not enabled - Not connecting (Try enabling auto-connect on the ICD2 settings pages.) Downloading Operating System Connecting to MPLAB ICD 2 ...Connected Setting Vdd source to MPLAB ICD 2 ICDWarn0020: Invalid target device id...
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    reconfigurable processor

    Ooops, I thought Nokia uses ARM architecture with AMBA bus controllers, not Intel architecture! Quite interesting... How did you get this info? Added after 6 minutes: Reconfigurable processor is a nice paradigm for new processors architecture. Imagine you can build your own instruction set...

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