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Re: PLL application
Hello hysamir,
suppose if u need mutiple frequenices.like in a transimitter u have to transmit data with various frequeincies( u need to allocate different channles for diffrent users), there how can u use a crystal osccilator which produce single frequency. and more ever...
regions of operation in cadence
Hello,
There is one simple method to check component values(Vdsat,gm,Id,Cgs,Cgd,........).first peform DC analysis.after that open caliculator.there select (op) button in caliculator which is operational parameters.after clicking on (op) button a new window open...
hello,
I have used that signal and i did simulations too. actually i need random signal for Clock anda Data recovery circuits there the width of 0 and 1 should be same.i need a siganl like 0001111000111100011. like that in using Vpwl it is difficlut to produce random siganl with some frequency...
Hello friends,
I have small doubt.when we simulationg digital gates in cadence.which symobl in cadence should we use for producing a random data(suppose we use Vpulse for pulse signal,what should we use for random data).i used input data as a pulse it is giving results.but for random data...
oscillation time
Hello paulux,
i am not looking for startup time.suppose if we run transient analysis in cadence.for how long it should oscillate to work properly
oscillator ckt
hello guys,
may be it is simple but i am confusing a lot..if we run transient analysis for an osiccalltor.if it is working properly how long it should ocsillate(ex 1u..).an ideal oscillator should oscillate infinite time .but a negative gm oscillator to work properly how long...
negative gm
Hello guys,
i was confusing about the operationg regions of active crcuit used in the implementaion of negative resistance in a LC VCO. can u guys explain operating regions of transistors with respective to amplitude. i mean when they enter in to sat,triode,cut off,and for steady...
german universities vlsi
Hello Guys,
It is really funny u guys r comparing german universities with unknown andwith the institutes runs for money .it is ridiculous.may be IIT s worth (only 2 r 3).please dont compare with veda,ttm...( institutes runs for money).in some german universities...
Hi,
In a PLL first of all it should try to make VCO frequency equal to that of the reference frequency.after that it decrease phase difference to zero. so that PLL locks. if the difference between ref. frequency VCO frequency higher than certain level PLL fails to lock.in this case we need...
vco specifications
Helloo savithru,
first u need to maintain differential pair transistors in saturation .for that u need to have common mode level between min and max levels.for min and max values go through
Desigon of analog integrated circuits by razavi.
and for highr swings voltage drop...
Hello Suria3,
The equation (Ron = 1/λIds ), u have given is valid when we consider channel length modulation.(i.e) the resistance when pinchoff occurs.at pinchoff drain current is more than in saturation .so i think u r statement on resistence at saturation is not valid . and morever the...
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