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Hi all, I am new to digital design. shown in the figure there is an 'addr' signal which is generated by some state machine. I want to sample the input data 'data_rec_in' with one clock cycle delay. Below is the code for the block.
Hi barry, thanks for your reply. you are right I should have posted the test bench too. Anyway I was able to solve the problem it was some reset timing issue in the testbench.
Hi,
I am trying to simulate some design. The pre-scalar in the design was working fine with the top level test bench. now I have instantiated another block in the test bench which configure the prescalar but pre-scalar generates a fatal error during simulation. When I try to load the counter...
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