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my altera MAxII CPLD has internal pull-ups :-)
But when I activate the pull-up for my signal, this is not accounted in the gate level simulation. Do you have any ideas why?
edit:
I found a solution: Do Altera simulation models support the programmable internal weak pull up resistor?
Yes, a pull-up would help me, but the circuit board design is already done and my CPLD can not integrate a pull-up resistor in the IO buffer. Please can you point me to a solution to detect the "unconnected inactive" state?
Hello,
I have a state machine that should switch on an external input signal. My problem is that the input signal maybe not driven by any device, so it's value is 'Z'. How can I avoid that my state machine switches to an undefined/unintended state? It is possible to check for 'Z' values in a...
Re: Delta Delay
Hello,
I have an advance question about delta delay.
I've developed a circuit in VHDL which does only contain combinatorial logic with an (unavoidable) internal feedback. In simulation it happens that the output signal needs 3 delta delays to stabilize.
time x+1: '1'
time x+2...
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