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Thanks! I was not setting output_delay and so no matter how much load capacitance I put in, the output delay requirement was always satisfied I think.
I put in a set_output_delay and now depending on the load capacitance, Design Vision complains about negative slack sometimes.
But my cells are custom small sized cells built in IBM 32nm and characterized by me using the Encounter Library Characterizer. Does this mean that during that characterization I messed up something?
What should I see when I increase set_load............do I see some slacks not being met...
I am synthesizing some designs using my own custom cells. I am trying to see how different parameters like clock and load affect the synthesis and / or timing.
The issue is, no matter what I do to the set_load parameter, my synthesis never complains or never reports a SLACK violation. However...
Hi,
I am trying to get a DFF characterized through Encounter Library Characterizer and am having problems with a DFF. First, I have successfully generated ECMS timing information for combinational gates. I needed to write gate files to make the tool identify the gate. Now I have a resettable...
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