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Recent content by Richard Divakar Vemagiri

  1. R

    I/O Voltage Rail means?

    What do you mean by 'I/O voltage rail'?
  2. R

    FFT(8-point butterfly) simulator

    Hi, Can anybody help me out with finding an FFT simulator. I am looking for some kind of a simulator for an 8-point FFT butterfly model, where I can give in inputs and get the outputs. I am working on an FFT VHDL code and would like to check my results using the simulator instead of manually...
  3. R

    Complex numbers in VHDL

    Hi Sckoarn, Thanks for that help. I'm actually not familiar with the differences among bit_vector, std_logic_vector and signed. Can you just tell me how these three types differ? Richard.
  4. R

    Complex numbers in VHDL

    Hi Sckoarn, In my code, 'p' is a variable. So i tried as p:=p sra 1;. Still i am getting the same error - near "sra": expecting <= or :=. Please let me know how to correct this, if possible. Thank you.
  5. R

    Complex numbers in VHDL

    Hi, I want to perform a right shift operation using the 'sra' keyword in VHDL. I have a signed bit vector of size 65 and i need to perform sra operation on it. I wrote as - p sra 1. I'm getting an error when I'm compiling saying: near "sra": expecting <= or := Can you help me out in knowing what...
  6. R

    Complex numbers in VHDL

    Hi, I'm trying to write an FFT VHDL code and would like to know how i should be dealing with complex numbers in VHDL... Please help me out.. Thanking You, Richard Divakar Vemagiri.
  7. R

    using port arrays in process block

    Hi TrickyDicky, Thank you for your post. But, I find X'range not working as the way you told it will be. I give 'X' a std_logic_vector(0 to 2) and say X'range for the loop variable 'i', it doesnt work. But instead if I put "for i in 0 to 2 loop", it works. Should I include any library or do...
  8. R

    using port arrays in process block

    Hi, I would like to know what value 'i' takes in this code: function CONV_INTEGER(X:std_logic_vector) return integer is begin for i in X'range loop --- Consider the value passed to 'X' is of type std_logic_vector(0 to 2); Thank you.
  9. R

    using port arrays in process block

    In fact, this is one of my projects that i need to finish within 2-3 weeks. I don't know if i can spend time learning VHDL first, and then try implementing it!!!
  10. R

    using port arrays in process block

    Hi TrickyDicky, Thank you for ur reply. I am in fact, trying to write a VHDL code for an 8 point decimation in time FFT algorithm (radix-2). The code that i showed u is to bit-reverse the positions of elements in the array. Can u suggest me a way to do it? I am not able to simulate the code...
  11. R

    using port arrays in process block

    Hi TrickyDicky, I didn't get any errors. I compile the code, and it says that compilation was successful. I'm using 'ModelSim PE Student Edition 10.0' for simulating. So after compilation, i click on 'Start Simulation' and everything works well. Now wen i force values into the 'input' array and...
  12. R

    using port arrays in process block

    package pck is type my_input_type is array(0 to 7) of integer; end pck; package body pck is end pck; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_textio.all; use work.pck.all; entity fft is port( input: inout my_input_type...
  13. R

    using port arrays in process block

    hi permute, sorry for getting back late. but thank you for ur reply. In fact, i wasn't clear about how u wanted me to do that package stuff. Can u just tell me how to write a package block, and where i should place it in the text editor? Sorry, but I'm new to VHDL and im' trying to learn...
  14. R

    using port arrays in process block

    declaring port as array Hi, plz help me with this.. entity fft is port(input: in array(0 to 7) of integer); end fft; Error - near "array": expecting STRING or IDENTIFIER or << or '(' I'm not able to understand wat i should modify.. plz do let me know...
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