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Recent content by refugee

  1. refugee

    Is there any way to combine WaveView and Cadence ADE together

    Dear all, Is there any way to combine WaveView and Cadence ADE together? The follow is my workflow: 1. use cadence ade to generate hspice netlist 2. use hsipce to simulate 3. use waveview to check the simulation results when the simulation file is big, it's suffering to wait for the results...
  2. refugee

    how to design a low offset error amplifier

    Hi, all How could I design a pretty low offset error amplifier (offset lower than 500uV)? Does it possible to using an autozero structure? Thanks
  3. refugee

    NMOS LDO Stability Problem

    Hi,all For NMOS LDO, we usually thought it intrinsic stability. And I'm sure for high load, the LDO is stability. But how about light load, or no load? For that condition, the output shows a low frequency pole. So, there are two low frequency poles, and it's hard to make good phase margin. So...
  4. refugee

    What does butting tap means

    This is a definition of layout, so is butting tap the same as body connection? Or could you pls tell me what'sbutting tap. Thx
  5. refugee

    fresh to install Hspice on linux...

    first you need a installer to install the common and Linux file. After you finish the install, you need configure your shell configuration file. (bashed or cshrc ) you should specify the hspice path and license path
  6. refugee

    how to plot (gm/Id) vs Id/Is for aMOS device

    You can draw this curve by running a DC analysis (swept the Id current). Suppose you want to plot the curve of M1, you need write a file like this: save M1:opponent Then you should include this file in your lib. After running the DC analysis, you can see the gm vs I'd curve in simulation results.
  7. refugee

    Effect of W < L for a MOSFET in layout and later stages

    May be you should specify your problem. I dont think there arent any problem for w<l misfit itself.
  8. refugee

    ESD problem of mos cap between vin and ground.

    Thanks for your reply, prcken. The vin pad is the power supply pad. I don't know what's the different between the nmos and pmos cap for this application. In our design, we usually use the ggnmos structure as the ESD device. I'm a little worried about that the gate of nmos cap might be...
  9. refugee

    ESD problem of mos cap between vin and ground.

    During low voltage design, we would like to connect a cap between vin and ground to clean the power supply. And if we use a nmos as the cap, how could we protect its gate? I have draw a pic to illustrate the question
  10. refugee

    How to design a HV start-up circuit

    Please forgive me I did not make it clear. Let's say that I need to design a boost converter. Vin=5~30V. So, I need design an internal power supply block. In this block, I designed a constant gm to generate current. So, I need a start up circuit. But I don't know how to design a start up...
  11. refugee

    How to design a HV start-up circuit

    I'd like to design a HV start-up circuit with zero static current. Does it possible? Somebody told me that it's an impossible task.
  12. refugee

    how to compensate a led driver

    I need to design a boost led driver with a current source. So, the feedback factor equals to 1. and the switching frequency is 100k to 1MHz. So, I wander if it's possible to compensate this boost inside the chip.
  13. refugee

    What's the advantage of constant off time

    I'd like to know what's the advantage of constant off time control method contrast to other control method ( constant on time and pwm method ). And it's appreciated if any one could tell me the optimized relationship of the off time and working parameters (such as VIN, VOUT, ILoad...)
  14. refugee

    How to compensate a large current ldo?

    Maybe this forum is not allowed to post a paper. So, if possible pls send me a email: chenjun77 at gmail.com

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