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Recent content by rca

  1. R

    Concise tutorial about how to run Synopsys tools from RTL to GDS?

    If you know the ASIC word, as you mentioned , you understand the row is not define and the tool cannot place any std cell... Read the documentation and start by doing a simple synthesis to then place this netlist... and the following steps.
  2. R

    post sim without sdf

    my question was to trig an analyze by qqxiu to understand the diff...
  3. R

    Mismatch between SPEF file generated by StarRC and the verilog netlist

    1- importing SPEF, will just confirm the sign-off STA inside innovus (tempus call in background). Personally I prefer to do that inside a sign-off timing engine (tempus or primetime), also depend of the foundry which sign-off STA is "approved". 2- in any case, adapting the RC scale factor is...
  4. R

    post sim without sdf

    do you clarify the differences between a RTL and a postsim netlist? That should help.
  5. R

    Gate level simulation issue on questasim

    And to complete "ThisIsNotSam", this model can be populated by your ROM C code compile and modify in the correct format.
  6. R

    [Cadence Innovus] Error in multi-thread placement

    well in this case Cadence support is here for that kind of situation.
  7. R

    Mismatch between SPEF file generated by StarRC and the verilog netlist

    right using Innovus with high extraction accuracy increased the runtime, so the trade off is to update the R/C factor to be close with less run time penality. The "signoff" innovus extraction can be used to do a pre-eco hold/setup, but I always prefer to used the ECO given by PT into innovus...
  8. R

    Mismatch between SPEF file generated by StarRC and the verilog netlist

    StarRC has a flow you can provide the netlist as input, no need of v2lvs. first question, from the foundry which RC tool is signoff? This signoff-spef should be used to provide the factor versus the Quantus-Innovus extraction tool (no the signoff one) to adapt the R/C calibration factor.
  9. R

    VHDL testbench SDF file annotation problem

    well the error message seems clear, hope your try more than one time...
  10. R

    measure power using PTPX time_based mode

    what do you mean the "time point of the value"? what do you expect?
  11. R

    Regarding svf file in formality

    can you remind what SVF file contain?
  12. R

    Simulation Mismatch between systhesis results in Design compiler

    as rise by ThisIsNotSam, LEC is here to validate the netlist post synthesis is identical to the RTL, never rely only on the TB. Both post synthesis netlist (with any option if both RTL are identical) must be LEC, if not, contact Synopsys.
  13. R

    Mismatch between SPEF file generated by StarRC and the verilog netlist

    StarRC can also read the netlist verilog, no need to go through the v2lvs flow. It's also good to correlate the innovus spef versus the StarRC spef with osctrich for example which will give the R/C correction factor to use in Innovus while RC view are read in the mmmc.

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