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It's just a push button they connected to a PL single-ended input. You can use it for anything. They decided to call it CPU_RESET. I use it to reset my PL logic.
r.b.
I did have a look at this document. This is not a simple exercise for someone with your apparent level of Verilog knowledge. This is an implementation of scalable parallel ternary CAMs, and Figure 3 is only a vast simplification of the actual block you would have to deliver. Figure 4 below it...
Depending on the firmware of your printer, or your slicing software, it may be possible to pause a print. change filament and resume the print with the new filament. With printers that understand g-code, you can modify the g-code by hand with the appropriate commands to pause, retract and...
Re: how spi decide when to receive(miso) and when to transmit(mosi)
The datasheet for the slave device will tell you exactly what to send to the slave and how/when the slave will respond to the transfer.
r.b.
To add to some of the comments above, other reasons for a dual extruder are for multi-color prints, and also for using the second extruder to print dissolvable support structures when printing an object with overhangs.
As for build volume, clearly that is based on the objects you want to...
By removing the reg from your definition of sclk, it defaults to a wire. Sclk must be a wire because you use the assign statement to assign sclk to sclk_sig. Assign is only used for wires.
r.b.
From personal experience, I can tell you that if you accidentally use a DC adapter that outputs a higher voltage than is specified, the power LED will blink on a Xilinx Spartan development board. In my case, going back to the proper charger stopped the blinking. Unfortunately the overvoltage...
In AXI4 , VALID and READY signals are used as flow control on each channel, with the provider of data on the channel asserting VALID to let the consumer of data know it has data to send. On a Xilinx FIFO, the EMPTY flag serves the same purpose. It lets the consumer of the data know whether or...
You really ought to read Xilinx document PG057, which describes the AXI4, AXI4-Lite and AXI4-Stream interfaces to the Xilinx FIFOS.
Table 1-8 explains that the BVALID signals are used as EMPTY flags. So if it is not asserting, then you are attempting to read from an empty FIFO.
r.b.
You should obtain and read the SI5338 Reference Manual. Section 10.4 makes mention of a PAGEBIT field in one of the registers which is used to access registers with addresses greater than 255.
r.b.
And to add to xtcx's comment, MATLAB's instrumentation control toolbox can be used to transfer data in many formats, including Ethernet and serial, between MATLAB and an FPGA.
I've never used this device, but in the datasheet I am looking at, in Section 5, it shows that you need to send the slave address, then the register address, then the data, when you do an I2C Write.
r.b.
Thanks again for the help.
I was wondering about that myself when I was reading it. The mass of the parts is so small, and their center of gravity is so close to the board that it would seem they would not be affected as much by vibration and shock.
r.b.
Hi all
Thanks for the replies!
Yes, the product will have to go thorough all of the tests that ads-ee listed. I apologize for for not being clearer.
I appreciate the info on EMI and board and component choices. I knew that mil-spec parts used SMT but a lot of the info I read raised...
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