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Recent content by raymond_luo2003

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    How to stream multiple GDS cells into one library in once

    stream in multiple gds files Hi, all, I got one standard cell library from TSMC. The library has more than 200 small GDS, INV1.gds INV2.gds ... NAND1.gds ... I only know to stream in GDS into my library one by one in Cadence, but it will take very long time. Could anyone advise me how to...
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    CDR when eye open with only 0.5UI

    Dear all, I really wonder the eye diagram definition in most serial link standard such as SATA, 1394 and USB2.0. I understand the eye closure is decided by deterministic jitter and random jitter which are above jitter corner frequency. Also I understand those high frequency jitter is not...
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    Customiz layout done by design engineer or layout engineer?

    Dear all, A simple question but confuse me lot! Recently our company get great debating on this topic: shall we recruit customer layout engineer or not???? Some design engineers think it is will need lots effort if the layout job done by layout engineer isn’t good enough, then design...
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    Is Assura good enough for 0.13/0.18um CMOS verification?

    Dear all, It seems many mixed-signal design teams select Calibre for 0.18um/0.13um Physical verification. Calibre look like a golden tool. Unfortunately, my situation is a bit different. Our boss want buy all the mixed-signal EDA tool from Cadence, the question become is the Assura is good...
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    Why Mentor Mixed-signal tool?

    ezwave mentor Dear All, I am a mixed-signal design engineer. I have been used Cadence tool and Synopsis tool for high speed analog IC design and mixed-signal simulation for quite while. Recently, things is going to change: Our boss want to change all the analog/ mixed-signal tool from...
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    Cable characteristic, pre-emphasis and post equalizer

    +equalizer +emphasis Dear all I need your help regarding on cable characteristic. Does anyone implement pre-emphasis and post equalizer in USB (or other SerDes Gigabit Ethernet or 1394B) transmitter and receiver respectively? If yes, what's the cable characteristic of short co-axial cable, say...
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    How we select PRBS sequence for BER test in SerDes? 2E23-1?

    prbs 2e7 prbs 2e7-1 Dear all, I read many papers regarding on the BER test of SerDes link. Different papers use different PRBS sequence 2E7-1; 2E11-1; 2E15-1; 2E23-1 to test their BER. For a same link, different PRBS will result in different BER, e.g. 10E-12 or10E-7. Does anyone can help me...
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    Virtuoso Layout Editor VS. Virtuosu XL Layout Editor

    cadence virtuoso xl layout Dear all, I would like to get your suggestion on which tool is sufficient to do the layout job for an experienced layout engineer, say, more than 5 years hands on experience. Virtuoso Layout Editor has PCELL feature, while Virtuoso XL Layout Editor has extended...
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    WHy always 4:1 MUX or 1:4 DEMUX in CDR?

    demux architecture used in cdr Dear all, There seems almost every high speed SerDes got 8B/10B encoder in high speed link or optical link, so the parallel data got the 10 bit buswidth. I just wander why there is no particular paper mentioning about the 10-phase sub-rate phase detector...
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    Bang-Bang Phase detector or Linear phase detector in CDR

    Dear all, Regarding on the Bang-Bang type and Linear type phase detector for Clock Data recovery application, which one is better? It seem bang bang type got large jitter, but with inherent retime data output. Linear type phase detector have better jitter performance while it suffer from the...
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    Multi-phase detector in CDR circuit; Not half rate or full r

    Re: Multi-phase detector in CDR circuit; Not half rate or fu Dear sutapanaki Thank you indeed. I 'd like to explain my system clear. I have to build a 1GHz data rate SerDes in one chip. And I have a 100Mhz+/-100ppm local reference x'tal clock on this chip. Obviously, the 10:1 ratio is due...
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    Multi-phase detector in CDR circuit; Not half rate or full r

    Dear all, Recently I got a task to design a SerDes with around 1GHz data rate. The tranmitter got a 100MHz local clock, and the the receiver got a similar but with a slight difference local clock, say 99.99MHz. So I have to use a CDR in my receiver to extract the clock information from the...
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    How to solve DLL false locking

    Thanks all your reply! My architecture have 4 phases clocks. As for the setting the delay of this DLL less than 2phi at initial stage, I agree with that. But how about the DLL got big noise at half way of operation, then the DLL lost the lock, then the DLL got chance to false locked to a 4Phi...
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    Preemphasis and equalizer in the SerDes design

    serdes pre-emphasis equalizer Dear all, I am working on the high speed SerDes design. I got some papers which mention about using the pre-emphasis and post-equalizer to improve the eyediagram at receiver side which is attenuated by cable loss. Altough that makes sense to use those types of...
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    Why we need Viterbi Decoder in high speed link?

    Dear all, I am doing high speed SerDes stuff for 1394B PHY. Currently I am reading a lots of papers, and trying to draft my Serdes architecture for this PHY. I got very much confused there is a few of papers mentioning about the Viterbi Decoder, which seems to help receiver of SerDes...
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