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Recent content by ravipandu46338@gmail.com

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    [SOLVED] Help needed in Interview Question!!

    Hi Sakthikumar, Just go through the following links http://digitalelectronics.blogspot.in/2010/05/backend-physical-design-interview.html http://asic-soc.blogspot.in/2008/03/backend-physical-design-interview.html **broken link removed**. http://vlsisystemdesign.com/kunal58625/...
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    [STA] SetUp/Hold Violation fix scenarious

    By considering setup fix,i said it...,you just go through the below answer (buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise we try to fix setup voilation with the sizing of cells; now just assume that you must insert buffer !) Near to capture...
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    [SOLVED] Help needed in Interview Question!!

    Tcq+Tcombi<=Tclock period-Tsetup-tskew 2ns+3ns<=Tclock period-1ns-1ns 2ns+3ns+1ns+1ns<=Tclock period 7ns<=Tclock period Frequancy=1/Tclock Period F=1/7*10-9
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    Why we fix SETUP Violations and then fix HOLD violations

    Hi dftrl, Setup timing analysis is done at the stage of placement because at the stage of placement if there is any setup violations then it is fixed only by making changes on data path(like inserting buffers,using LVT cells,cell upsizing) but we don't touch the clock path and at this stage...
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    [STA] PVT vs OCV - are the same in terms of STA?

    Yes,You are right....,it should be vice verse by mistake i wrote it like that...,
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    [STA] SetUp/Hold Violation fix scenarious

    Because there may be other paths passing through or originating from the flop nearer to lauch flop. Hence buffer insertion may affect other paths also. It may improve all those paths or degrade. If all those paths have violation then you may insert buffer nearer to launch flop provided it...
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    [SDC] What type of timing constrains stored @SDC?

    SDC file contains clock definition,generated clock,clock latency(Source+Network)latency,Clock uncertainity(Skew+Jitter,Margin),False path,Multi cycle path,Multi frequancy path,crtical path,half cycle path,input delay,output delay,min,max delay
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    [STA] PVT vs OCV - are the same in terms of STA?

    PVT Process voltage Temperature If process increases then cell delay increases If voltage increases then cell delay decreases If temperature increases then cell delay increases Due to the variations in PVT some timing derating factor is provided for on chip variation by the vendor to get...
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    What is the difference between a .lib and a .db file used for Design Compiler?

    .lib and .db provides timingfunctionality,power information of standard cells and macro cells Logical DRC's Max Tran Max Cap Min/Max Fanout The only difference is .db is encrypted(ASCII) format
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    difference between pins and feed through

    Feed Through:-Feedthrough is nothing but a net will be going through your block but it's lunch and capture flop will not be in our block that is called as Feed Through Pin:-Pin is nothing but a connecting point
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    [STA] SetUp/Hold Violation fix scenarious

    No we insert a strengthen buffer near to the input pin of capture flop
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    Need of Endcaps in design?

    end cap cells are defined at the end of design. These are physical cells which do not have any functionality These cells are basically used at the time fabrication not to damage the cells which are defined at the end of the row these endcap cells are used...., Thanks & Regards, D.Raviteja
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    [STA] SetUp/Hold Violation fix scenarious

    Register to Register path Setup can be fixed by 1.Upsizing combinational cells that are nearer to capture flop 2.using LVT cells 3.Inserting buffers Hold can be fixed by 1.Downsizing combinational cells that are nearer to capture flop 2.Using HVT cells 3. Inserting delay buffers In Input to...
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    How skew value and max insertion delays are calculated?

    Re: clock skew and timing Skew is the difference between the arrival times of clock to the clock pins of register insertion delay:- The delay from clock definition point to clock pin of register if skew is maximum then timing will not be met....,that is the reason why skew should be minimum...
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    Trial Route & Detail Route

    Hi all, By default timing analysis is based on a "Virtual Route" Which is an estimation of Resistance, Capacitance values of all metal layers Thanks & Regards, D.Raviteja
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