Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Ravi Tej

  1. R

    How to write a Testbench in VHDL or Verilog for ISCAS benchmark Circuit.

    Can anyone help me with how to write a testbench for ISCAS benchmark circuit in particular C6288 as I need to generate a VCD file to get the V-file of the benchmark circuit using Design complier. Regards, Ravi Tej
  2. R

    Designing an Operational Transconductance amplifier(OTA) using LTspice.

    Hi, I am new to LTspice, and i would like to build an operational amplifier using it, but im having problems with biasing the transistors such that I can expect a desired voltage gain. Also, how can I find the parameters such as 'K' from a model file which specifies the parameters. Many...
  3. R

    Download LTSPICE for MAC Book Pro

    Hi, Can anyone help me with a site where I can get LTSPICE for MAC. Regards. Ravi Tej.
  4. R

    Timing analysis in Cadence encounter

    Thank you for the reply.
  5. R

    Regarding Synopsis CAD tools.

    Hi, I am new to CAD tools and would like to learn Synopsis. Can anyone help me with material which can guide me through the basics. Thanks & Regards, Ravi Tej.
  6. R

    Timing analysis in Cadence encounter

    I am new user of cadence, n I would like to get the critical path delay from encouter, can anyone help me with this.
See more

Part and Inventory Search

Back
Top