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Recent content by rananazzal

  1. R

    interface between 2 FPGA via RS232

    please i want to understand what is the purpose of this part in the receiver code always @(posedge clk) if(Baud8Tick) begin if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 2'h1; else if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 2'h1...
  2. R

    interface between 2 FPGA via RS232

    yes , receive and async_tranmitter are modules in different files in my project this code is s top level code and (sw1) is an input assigned to one of the switches in the FPGA , if the value of sw1 (or the input from switch is 1 ) the receive code is called, and if sw1==0 the...
  3. R

    interface between 2 FPGA via RS232

    i wrote this code module top_rs232(sw1 , iCLK ) ; input sw1 , iCLK ; if(sw1==1) begin receive r(.clk(iCLK)); end else begin async_transmitter t(.clk(iCLK)); end endmodule and after compilation there is an error --->>> Error (10170): Verilog HDL syntax error at...
  4. R

    interface between 2 FPGA via RS232

    yes i did , i test the 2 codes with the hiperterminal independently and the result is correct !! but how can i make this cable cross???
  5. R

    interface between 2 FPGA via RS232

    i test my codes using a terminal program ,and it is work correct but when i test these codes in the FPGA , the receiver fpga always light 8 leds regardless of the data i send , why??? i use rs232 cable (male to male ) , i want to know if i need to change the connection of the wires inside...
  6. R

    interface between 2 FPGA via RS232

    no how can i do it ??
  7. R

    interface between 2 FPGA via RS232

    the transmitter code is module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy); input clk, TxD_start; input [7:0] TxD_data; output TxD, TxD_busy; parameter ClkFrequency = 50000000; // 50MHz parameter Baud = 115200; // Baud generator parameter BaudGeneratorAccWidth = 16...
  8. R

    interface between 2 FPGA via RS232

    this is my verilog codes file:///C:/Users/uni/Desktop/rs232/async_receiver.v__.htm file:///C:/Users/uni/Desktop/rs232/async_transmitter.v__.htm and no , i did not test it with the hiperterminal !! what is the max232 chip ??? in the receiver FPGA , 8 leds must light or not depends on the...
  9. R

    interface between 2 FPGA via RS232

    hi I m trying to communicate between two FPGA board through rs232 , a 1 byte is being transmitted from the board1 with a baudrate say 115200. and the other FPGA is also configured to receive 1 byte at the same baud rate, when 1 byte is arrived to FPGA it is arrive wrong , but when i test it...
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