interface between 2 FPGA via RS232

[rananazzal]

hi

I m trying to communicate between two FPGA board through rs232 ,
a 1 byte is being transmitted from the board1 with a baudrate say 115200.
and the other FPGA is also configured to receive 1 byte at the same baud rate,


when 1 byte is arrived to FPGA it is arrive wrong , but when i test it using modelsim the result is correct

please help me to know what is the problem
thanks in advance.

 

[Alex02]

Did you test it with the hiperterminal or a similar program first? If not I'd do that first. If it is working with the hiperterminal it shouldn'd have any problem.

 

[TrickyDicky]

why not post your HDL code here? have you got any logic clocks? those can be the source of many problems.

 

[kirangowle]

Have you used max232 chips?. What could be the distance from one board to other.

 

[lucbra]

And maybe, you could try at lower baudrates first - say 4800Bd)

What do you receive?

 

[engrMunna]

check you endianness...usually people forget to cater for that and the board that you are using is it able to drive the length of the cable you are using? best thing would be to check with hyperterminal

 

[rananazzal]

this is my verilog codes

file:///C:/Users/uni/Desktop/rs232/async_receiver.v__.htm

file:///C:/Users/uni/Desktop/rs232/async_transmitter.v__.htm


and no , i did not test it with the hiperterminal !!

what is the max232 chip ???


in the receiver FPGA , 8 leds must light or not depends on the 1 byte that receive
but when i send 10101010 for example the 8 leds light !!! why ????

 

[TrickyDicky]

you didnt post your code, just links to them on your local drive

 

[rananazzal]

the transmitter code is

module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;

parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 115200;

// Baud generator
parameter BaudGeneratorAccWidth = 16;
parameter BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;

// Transmitter state machine
reg [3:0] state;
assign TxD_busy = (state!=0);

always @(posedge clk)
case(state)
4'b0000: if(TxD_start) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; // start
4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
4'b1111: if(BaudTick) state <= 4'b0001; // bit 7
4'b0001: if(BaudTick) state <= 4'b0010; // stop1
4'b0010: if(BaudTick) state <= 4'b0000; // stop2
default: if(BaudTick) state <= 4'b0000;
endcase

// Output mux
reg muxbit;
always @(state[2:0] or TxD_data)
case(state[2:0])
0: muxbit <= TxD_data[0];
1: muxbit <= TxD_data[1];
2: muxbit <= TxD_data[2];
3: muxbit <= TxD_data[3];
4: muxbit <= TxD_data[4];
5: muxbit <= TxD_data[5];
6: muxbit <= TxD_data[6];
7: muxbit <= TxD_data[7];
endcase

// Put together the start, data and stop bits
reg TxD;
always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free

endmodule

---------- Post added at 15:33 ---------- Previous post was at 15:33 ----------

the receiver code is

module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
input clk, RxD;
output RxD_data_ready; // onc clock pulse when RxD_data is valid
output [7:0] RxD_data;

parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 115200;

// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high)
output RxD_idle; // no data is being received

// Baud generator (we use 8 times oversampling)
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
parameter Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];

////////////////////////////
reg [1:0] RxD_sync_inv;
always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup

reg [1:0] RxD_cnt_inv;
reg RxD_bit_inv;

always @(posedge clk)
if(Baud8Tick)
begin
if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 1;
else
if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 1;

if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 0;
else
if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1;
end

reg [3:0] state;
reg [3:0] bit_spacing;

// "next_bit" controls when the data sampling occurs
// depending on how noisy the RxD is, different values might work better
// with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==10);

always @(posedge clk)
if(state==0)
bit_spacing <= 0;
else
if(Baud8Tick)
bit_spacing <= {bit_spacing[2:0] + 1} | {bit_spacing[3], 3'b000};

always @(posedge clk)
if(Baud8Tick)
case(state)
4'b0000: if(RxD_bit_inv) state <= 4'b1000; // start bit found?
4'b1000: if(next_bit) state <= 4'b1001; // bit 0
4'b1001: if(next_bit) state <= 4'b1010; // bit 1
4'b1010: if(next_bit) state <= 4'b1011; // bit 2
4'b1011: if(next_bit) state <= 4'b1100; // bit 3
4'b1100: if(next_bit) state <= 4'b1101; // bit 4
4'b1101: if(next_bit) state <= 4'b1110; // bit 5
4'b1110: if(next_bit) state <= 4'b1111; // bit 6
4'b1111: if(next_bit) state <= 4'b0001; // bit 7
4'b0001: if(next_bit) state <= 4'b0000; // stop bit
default: state <= 4'b0000;
endcase

reg [7:0] RxD_data;
always @(posedge clk)
if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};

reg RxD_data_ready, RxD_data_error;
always @(posedge clk)
begin
RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received
RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 && RxD_bit_inv); // error if the stop bit is not received
end

reg [4:0] gap_count;
always @(posedge clk) if (state!=0) gap_count<=0; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 1;
assign RxD_idle = gap_count[4];
reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==15);

endmodule

---------- Post added at 15:41 ---------- Previous post was at 15:33 ----------

 

[lucbra]

Did you look at the signal travelling from FPGA1 to FPGA2 with a scope?

 

[rananazzal]

no

how can i do it ??

 

[prakashvenugopal]

Hi,

Assume you are sending the data with 9600 bps and sending the data of 0x55, you will get
104 us pulse in the TX output of 1st FPGA .

T = 1/9600 = 104.16 micro second

Hope this will help you.

 

[mrflibble]

I thought that code looked familiar. It looks to be the one from fpga4fun.

I use that in a few projects, and the verilog code works just fine.

How about reducing uncertainties? Just use one fpga and connect it to the PC using a terminal program. I see hyperterminal has already been suggested. At least that way you are reasonably sure about one side. Plus even if you are sending garbage, you usually get to see something providing clues.

Also, setting the baudrate low and just hooking up leds to RX and TX can sometimes help in debugging silly mistakes.

 

[rananazzal]

i test my codes using a terminal program ,and it is work correct

but when i test these codes in the FPGA , the receiver fpga always light 8 leds regardless of the data i send , why???



i use rs232 cable (male to male ) , i want to know if i need to change the connection of the wires inside the cable !!

thanx

 

[Alex02]

The cable has to be null modem, it means that the transmit and receive lines are crosslinked.

Did you test both FPGAs with the hiperterminal program independently ?

 

[rananazzal]

yes i did , i test the 2 codes with the hiperterminal independently and the result is correct !!

but how can i make this cable cross???

 

[mrflibble]

Crossover cable - Wikipedia, the free encyclopedia
Null modem - Wikipedia, the free encyclopedia

 

[rananazzal]

i wrote this code


module top_rs232(sw1 , iCLK ) ;
input sw1 , iCLK ;

if(sw1==1)
begin
receive r(.clk(iCLK));
end
else
begin
async_transmitter t(.clk(iCLK));
end
endmodule


and after compilation there is an error --->>> Error (10170): Verilog HDL syntax error at top_rs232.v(4) near text "if"; expecting "endmodule"

i cant understand what is the meaning of this error and how can i deal with it

please help me and thanx a lot

 

[mrflibble]

receive and async_tranmitter are modules right? They don't go between if statements like that.

What do you expect this to do in real hardware? As in, what hardware was it supposed to represent.

regardless, taking the follow 2 outside of any "if" like that will help:

receive r(.clk(iCLK));

async_transmitter t(.clk(iCLK));

Won't solve your functional problem (try some more ), but will solve the error.

 

[rananazzal]

yes , receive and async_tranmitter are modules in different files in my project

this code is s top level code and (sw1) is an input assigned to one of the switches in the FPGA , if the value of sw1 (or the input from switch is 1 ) the receive code is called, and if sw1==0 the async_transmitter code is called !!!!

all of this to make one FPGA can be sender and receiver