Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The code is as below !
module top;
wire[17:0]A[1:3][1:3]; // the matrices
wire[17:0]B[1:3][1:3];
wire[17:0]C[1:3][1:3];
wire[(9*18)-1:0] Abits; // bit-decomposed versions of the above
wire[(9*18)-1:0] Bbits;
wire[(9*18)-1:0] Cbits;
genvar i,j;
// set A and B...
Is this possible placing the if statement inside the genvar and for look because I want to check each element of an array zero or not ? And then assign specific function for the values if its zero or non-zero element? Because when I tried the above syntax its throwing an error "A is not a...
I was trying to recreate the program from c to verilog ! Since I am familiar with C language, I started writing in C at first. But now I need to implement this in a hardware so I was trying to write in verilog for fpga implementation. Any suggestions for converting C to verilog ?
I am writing program to add two sparse matrix to work in vivado 2016.2 and I am not able to get the output properly. If anyone is interested in helping me out, it will be a great help for me.
Following is the verilog code which i tried out/
This program should add two sparse matrix by finding...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
