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Recent content by rajsrikanth

  1. R

    UART (3v3 TTL) Isolator Chip

    u can use optocoupler for this kind of solution. based on the level translation.
  2. R

    [SOLVED] I am not sure if this is a resistor, can anyone confirm if it is resistor?

    A wire wound resistor is a resistor where a wire with a high resistivity is wrapped around an insulating core to provide the resistance Read more http://obrazki.elektroda.pl/2172496800_1418367769.jpg[/img]
  3. R

    Frequency range of TV, radio transmission in India

    for TV 585-698MHz Used for TV broadcast 87.5-108 MHz is used for FM radio broadcasts 3600-10000 Space research, radio navigation
  4. R

    what's the practical use of hilbert transform?

    Hilbert transform can be used for Sampling of bandpass signals for communication 3 AM-FM decomposition for auditory prostheses for system identification thanks and regards
  5. R

    Anyone have I2C Slave Verilog code?

    Re: i2c slave verilog please go through the fpga4fun site fpga4fun.com - Welcome regards srikanth
  6. R

    Xilinx 9.2i installation, unable to find the IP coregen option

    Re: Help regarding xilinx 9.2i installation check for ip udates available or reinstall the software again regards
  7. R

    system verilog for design 2nd edition by stuart sutherland

    Re: system verilog for design 2nd edition by stuart sutherla Attaching SV book good book regards srikanth
  8. R

    VHDL/Verilog code help!!!

    check for the site opencores.org useful one
  9. R

    I need any information regarding cpci

    help regarding cpci hi everyone iam going to use a cpci back plane for my board based on a processor and i need information regarding the cpci pls can anyone telll me the difference between the cpci and cpi(other than the connnector) in the design point of view what is the difference b/w...
  10. R

    help on ddr sdram- could not get the memory test passed

    sdram ucf mpmc hi everyone my ddr sdram is interfaced to virtex4 fx100 iam using EDK-POWERPC to configur the ddr sdram . iam using MT46V16M16TG-5T device . it is 16bit device. iam also using the ip core of MPMC for the ddr in edk i generated the ucf using MIG2.3 i have set the desired...
  11. R

    about delays in verilog #40 is 40 ns/s or 40 clock pulses?

    about delays in verilog hi everyone i want to know how the delay is taken in verilog like if we give #40 what does it mean. is it mean 40ns/s delay or 40 clock pulses delay. can any one help me on this isssue. regards srikanth
  12. R

    Is Verilog "While Loop" synthesizable ?

    while loop in verilog while is verilog is not synthesizable. i tried it. regards sri
  13. R

    Where can I find a VHDL UART example for testing rs232

    Re: rs232 and uart you can have a look at fpga4fun site www.fpga4fun.com regards srikanth
  14. R

    Verilog problem with building shift register which can have parallel or serial input

    Re: Verilog problem in this you dont have k initialized or taken as input. regards srikanth rajkumar
  15. R

    Ideas for a third year BTech project in VHDL

    Re: need help plz! check for some sites like open cores u can find many small or big projects in it. www.opencores.org regards srikanth raj kumar
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