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Recent content by rajrevanth61

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    How to calculate Delay in Cadence using the calculator

    Hello Sir, Thanks for the reply. If there are two signals then i have placed markers on two signals and calculate the delay by measuring the difference. But in this case there are three signals(2 input , 1 output). So On what combination(00-0, 01-1, 10-1,11-1) should I calculate the delay...
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    How to calculate Delay in Cadence using the calculator

    Hello Everyone, I have a OR gate for which i want to measure average and worst case delay using cadence calculator. How do i do this . I know the procedure if there is one input and one output as in the inverter But in my case there are two inputs and one output. How can i measure delay now...
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    Convergence problem with cadence spectre

    Hello everyone, I am trying to write a 2x1 multiplexer using the mems switch in veriloga. But when i try to simulate the circuit i am getting errors. ERROR (SPECTRE-11005): Matrix is singular (detected at `out'). ERROR (SPECTRE-16080): No DC solution found (no convergence). Here is my...
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    Does modelsim support verilog-a

    Hello Sir, Thanks for the reply. What are my options for simulating verilog-a code using the cadence software. I have full licensed cadence version 6.1.6. Does NC-verilog support verilog-a?
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    Does modelsim support verilog-a

    Hello everyone, I just wanted to know if MODELSIM supports verilog-a code? If it supports which version is it? Thank You
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    How to instantiate models in verilog-A

    Hello Everyone, I am new to the Verilog-A programming. I have a model for MOSFET switch written in verilog-a. Now I want to construct inverter by instantiating the mosfet model. How do I do this. Is the instantiating method same as the method used in verilog. Ex: mosfet mosfet_1(D G S B)...
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    Verilog-a model instantiation

    Hello Sir, Thank You for the reply. Can you please tell me what might be the correct way to declare VDD and GND..? Thank You
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    Verilog-a model instantiation

    Hello sir, I tried the same code of inverter instantiation with the mosfet as the switch(D G S B) by taking the code from the site which you referenced. Even then I am getting the same error. I think the syntax I used for defining VDD and GND is not correct. Can you please tell me the correct...
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    Verilog-a model instantiation

    Hello Sir, Thanks for the reply. I added vdd and gnd in the module statements and called them as electrical also. Even then I am getting the same Error. What might be the problem? module inverter(in, out, vdd, gnd); input in; output out; electrical in, out; electrical vdd,gnd; input vdd =...
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    Verilog-a model instantiation

    Hello Experts, I am new to use of Verilog a models . I have the code for mems switch using the verilog-a. Now I would like to instantiate the mems switch to work as a inverter. But I am getting error as below Code for inverter model instantiation is as below. (i have written this code after...
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    Verilog-A to Circuit Simulation Model

    Hello Experts, I am new to use of Verilog-A programming. I had question regarding the use of this language. I want to design the NEMS switch model using the Verilog-A model. Once I design this model will I be able to create a circuit simulation model of the NEMS switch which can be used as a...
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    Sram read operation using switches in pspice

    [moved] Sram read operation using voltage controlled switches in pspice Hi, Here is my code for SRAM for read operation implemented using voltage controlled switches, can anyone help me where I went wrong in the code. both BL and BLB are loosing there voltage levels. when i am trying to read a...
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    Sram read operation using switches in pspice

    According to the code I am not skipping any initial condition. and what should I do in order to have a effect on the data access switches. Please help me. I am stuck
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    How to design a switch in pspice using netlist with certain characteristics?

    Hello all, I would like to design a three terminal switch(similar to mosfet) which has the certain voltage, capacitance and switching speed . How do i do this .? Please help me, Any Leads would be of great help. Thanks in advance.
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    Problem with D-latch pspice netlist

    Hello Experts, I have a d-latch pspice netlist, when i try to simulate it Iam getting a clipped output that is for the input of 1v I am getting output as only 0.5v . what should I do inorder to get the full output voltage of 1v. q and qb are my output nodes. Please help me. *d latch vd d 0...
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