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Recent content by rahulkumarkhokher

  1. R

    Not able to open schematic for signal tracing after loading fsdb in verdi

    Hi All, I have compiled/simulated design/Tb with the switch/args as shown below : =================================================== -lca +vcs+lic+wait +v2k +vcsd -V +vcs+flush+log -sverilog +libext+.v+.sv +systemverilogext+.sv +systemverilogext+.svh -full64 +define+PURE=extern...
  2. R

    Strobe vs clock in ddr

    ok, Thats mean MCLK can not be used for read data, But MCLK can be used for write data(As ctrl drives MCLK and write data). then why strobe is used to write data into memory Thanks Rahul
  3. R

    Strobe vs clock in ddr

    HI All, Why strobe is required to sample data in DDR, That can be done with clock as well? As per DDR spec, dqs(strobe) to clock delay is also fixed(tDQSS), then why clock can not be used to sample data as synchronous circuits Please reply. Thanks an Regards, Rahul Kumar
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    use of latch for SRAM cell instead of flipflop

    Hi All, Why does latch is used as SRAM cell instead of flipflop? As latch is used as sram cell, why sram cell does not have race around condition? Thanks, Rahul
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