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Hi,
Yes, apologies, I have instantiated the module incorrectly and here is the rewrite.
module my_mod(a, b);
input a;
output b;
assign b = a;
endmodule
module my_mod_tst();
reg x;
wire y;
reg z;
my_mod mm(x, y);
initial begin
x = 1;
z = y;
if (z == 1)...
Hi,
Would like to ask how to transfer a value of an output from DUT to test bench?
I have the following code:
module my_mod(a, b);
input a;
output b;
assign b = a;
endmodule
module my_mod_tst();
reg x;
wire y;
reg z;
my_mod_tst mmt(x, y);
initial...
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