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Recent content by radwa5

  1. R

    [SOLVED] Synthesizing a 5-input AND gate, instead of three 2-input AND gates in xilinx ISE

    ok Thanks for your help, I got the idea
  2. R

    [SOLVED] Synthesizing a 5-input AND gate, instead of three 2-input AND gates in xilinx ISE

    I don't want this reduction, this leads to multilevel design and increased the time delay is there an option to synthesis the code as it is?
  3. R

    [SOLVED] Synthesizing a 5-input AND gate, instead of three 2-input AND gates in xilinx ISE

    My device can support the 5 input and 4 input AND gate (it is virtex 6 ) when I write a code for 5 input and gate in a project alone, run the code it synthesize it as 5 input AND gate. but using it in the carry look ahead adder code, they are synthesized as 2 input and gates
  4. R

    [SOLVED] Synthesizing a 5-input AND gate, instead of three 2-input AND gates in xilinx ISE

    Dear all, I wrote a code that contain 5 input and gate, but the ISE synthesis tool used three two input AND gates in 3 levels instead of only one 5 input gate in one level, What options can I change to synthesize my code using only one 5-input AND gate
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