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[SOLVED] Synthesizing a 5-input AND gate, instead of three 2-input AND gates in xilinx ISE

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radwa5

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Dear all,
I wrote a code that contain 5 input and gate, but the ISE synthesis tool used three two input AND gates in 3 levels instead of only one 5 input gate in one level,

What options can I change to synthesize my code using only one 5-input AND gate
 

andre_teprom

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I'm not familiar with logic design, but the question arises anyway: Is the requested 5-NAND gate available at the logic cells on the target device where you're synthesizing ?
 

TrickyDicky

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Either its done logic minimisation with surrounding logic, or your device has only 4 input luts.
 

radwa5

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My device can support the 5 input and 4 input AND gate (it is virtex 6 )
when I write a code for 5 input and gate in a project alone, run the code it synthesize it as 5 input AND gate.
but using it in the carry look ahead adder code, they are synthesized as 2 input and gates
 

TrickyDicky

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This has likely happened as logic reduction when the circuit is compiled.
 

radwa5

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This has likely happened as logic reduction when the circuit is compiled.
I don't want this reduction, this leads to multilevel design and increased the time delay

is there an option to synthesis the code as it is?
 

TrickyDicky

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Your assertion is unlikely, as the tools will try and meet the timing specifications you require. They will report if timing is not met in a synchronous design. An Asynchronous design is not recommended, as not only will the delay changed based on the logic, itself, it is also dependent on routing, temperature, voltage and the differences between parts.
 

barry

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Depending on the physical location of the gates, your 3-level logic might (probably is) faster than a single gate. As mentioned, the tool is going to try and meet timing and won't arbitrarily add more logic delay. Routing delay also figures into the implementation. If you've got a really dense design, the 3 gates might have been the best solution. But if you're hell-bent on using a 5-input NAND, then just instantiate it in your code with a KEEP (or similar) directive.
 

radwa5

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ok Thanks for your help, I got the idea
 

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