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I think I found the answer
Verilog-A allows parameterized bus widths for ports and signals.
but the Cadence Verilog-A implementation does not allow this: According
to Cadence Verilog-A reference v11.1 "parameter-sized ports"
are not supported.
Your modulator is unstable, the first filter output is going up as high as 50k. You should not put saturation blocks as a stable modulator should
limit the outputs of the filter.
You are already using delaying integrators in your loopfilter i.e 1/(1-z) = z^-1 / (z^-1 - 1) so you don't need an...
If you know your noise requirement then you should be able to determine the bias current in the amplifier as the two are related (More current -> less noise). This also gives your transconductances gm1 in the first stage. Then depending on your requirement on the gain bandwidth and the phase...
Hi
I'm trying to create an instance with a parametrized bus
in Verilog-A i. e. when I instantiate it in a schematic in cadence,
then there should be a parameter to determine the size of
the bus by clicking on the instance and pressing Q. The idea is to
avoid creating several instances with the...
Yeah I see what you are saying, one can picture an ideal inversion.
It is also possible to derive the voltage gain from vi2 to vo2 under the assumption
that vi2 = -vid/2 and vi1 = vid/2 (the exact opposite). The gain of
the amplifier from vi2= -vid/2 to vo2 is then the same as for the half...
Hi
Yes exactly, if your voltage and current are both sinusoids then you can show
by using the definition for average power that Pavg = Vrms * Irms * cos(a)
where a is the phase difference between the voltage and current and cos(a) is called the power factor. Then if a=0, the average power is...
Hi
Sure, fig 12.23 shows the fully differential op amp
and fig 12.24a shows its DM half circuit
BR
Added after 4 minutes:
Seems like the first figure wasn't uploaded.
Here i will try again.
Hi
Average power is defined as
Pavg = (1/T) * integ(v(t)i(t)) dt (limits: tstart - tstart +T).
Since the supply voltage is constant, aveage power in a ganeral voltage supply
with voltage Vdc is calculated using the definition:
Pavg = Vdc * (1/T) * integ(i(t)) dt (limits: tstart - tstart +...
Hi
I was reading chapter 12 page 836 in Gray Hurst Lewis and Meyer book.
In figure 12.24a the DM half-circuit for the fully differential opamp on the
previous page is drawn. The input signal is -vid / 2 and the output signal is
vod / 2 which means that the half circuit is inverting. However, my...
ct delta sigma and dt delta sigma
Hi,
I have modelled a 3:rd order 3-bit delta sigma modulator in the matlab-toolbox
and transformed it to continuous time. The continuous time modulator is modeled
in Cadence using verilog-A. I have checked the impulse responses of both loopfilters in cadence...
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